pef82902 Infineon Technologies Corporation, pef82902 Datasheet - Page 167

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pef82902

Manufacturer Part Number
pef82902
Description
4b3t Second Generation Modular Isdn Nt Intelligent Extended
Manufacturer
Infineon Technologies Corporation
Datasheet

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SRA
XCRC
RCRC
ITF
4.4.9
TIMR
Value after reset: 00
Data Sheet
Note: ITF must be set to ‘0’ for power down mode.
In applications with D-channel access handling (collision resolution), the only
possible inter-frame time fill is idle (continuous ‘1’). Otherwise the D-channel on
the S/T-bus cannot be accessed.
7
Store Receive Address
0 =
1 =
Transmit CRC
0 =
1 =
Receive CRC
0 =
1 =
Interframe Time Fill
Selects the inter-frame time fill signal which is transmitted between HDLC-
frames.
0 =
1 =
TIMR - Timer Register
CNT
Receive Address is not stored in the RFIFO
Receive Address is stored in the RFIFO
CRC is transmitted
CRC is not transmitted
CRC is not stored in the RFIFO
CRC is stored in the RFIFO
idle (continuous ‘1’)
flags (sequence of patterns: ‘0111 1110’)
H
5
4
read/write
153
VALUE
Register Description
Address:
PEF 81902
2001-11-12
0
24
H

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