pef82902 Infineon Technologies Corporation, pef82902 Datasheet - Page 70

• Manufacturer Part Number: pef82902
• Description: 4b3t Second Generation Modular Isdn Nt Intelligent Extended
• Manufacturer: Infineon Technologies Corporation

• Local D-channel source commences with D data transmission on IOM
• After D-channel data transmission is completed the controller sets the BAC bit to
• T-SMINT
• T-SMINT
Note: If right after D-data transmission the D-channel arbiter goes to state ’Ready’ and
2. Terminal Transmits D-Channel Data Upstream
The initial state is identical to that described in the last paragraph. When one of the
connected S-bus terminals needs to transmit in the D-channel, access is established
according to the following procedure:
• S-transceiver recognizes that the D-channel on the S-bus is active via D = ’0’.
• S-transceiver transfers S-bus D-channel data transparently through to the upstream
2.3.6
The deactivation procedure of the IOM
detecting the code DI (Deactivation Indication) the T-SMINT
transmitting DC (Deactivation Confirmation) during subsequent frames and stops the
timing signals after the fourth frame. The clocks stop at the end of the C/I-code in IOM
2 channel 0.
Data Sheet
T-SMINT
block all connected S-bus terminals (E = D).
it receives S/G = “0”.
ONE.
controller on IOM
IOM
the local D-channel source wants to transmit again, then it may happen that the
leading ’0’ of the start flag is written into the D-channel before the D-channel
source recognizes that the S/G bit is pulled to ’1’ and stops transmission. In order
to prevent unintended transitions to state ’S-Access’, the additional condition CNT
source may start transmission again (if TIC bus is occupied). This allows an equal
access for D-channel sources on IOM
â
2 is introduced. As soon as CNT
-2 bus.
Activation/Deactivation of IOM
â
â
â
IX S-transceiver transmits inverted echo channel (E bits) on the S-bus to
IX S-transceiver transmits non-inverted echo (E = D).
IX S-transceiver pulls S/G bit to ONE (’Ready’ state) to block the D-channel
â
-2.
â
56
n, the S/G bit is set to ’0’ and the D-channel
-2 interface is shown in Figure 30. After
â
-2 and on the S interface.
®
-2 Interface
Functional Description
â
IX responds by
â
-2 as long as
PEF 81902
2001-11-12
â
-