pef82902 Infineon Technologies Corporation, pef82902 Datasheet - Page 44

• Manufacturer Part Number: pef82902
• Description: 4b3t Second Generation Modular Isdn Nt Intelligent Extended
• Manufacturer: Infineon Technologies Corporation

2.3.2.1
The four controller data access registers (CDA10, CDA11, CDA20, CDA21) provide
microcontroller access to the 12 IOM
• looping of up to four independent PCM channels from DU to DD or vice versa over the
• shifting or switching of two independent PCM channels to another two independent
• monitoring of up to four time slots on the IOM
• microcontroller read and write access to each PCM channel
The access principle, which is identical for the two channel register pairs CDA10/11 and
CDA20/21, is illustrated in
description can be 1 or 2 for x, and 0 or 1 for y. The prefix ’CDA_’ from the register names
has been omitted for simplification.
To each of the four CDAxy data registers a TSDPxy register is assigned by which the
time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a
time slot from 0...11 can be selected. With the DPS (Data Port Selection) bit the output
of the CDAxy register can be assigned to DU or DD respectively. The time slot and data
port for the output of CDAxy is always defined by its own TSDPxy register. The input of
CDAxy depends on the SWAP bit in the control registers CRx.
If the SWAP bit = ’0’ (swap is disabled) the time slot and data port for the input and output
of the CDAxy register is defined by its own TSDPxy register.
If the SWAP bit = ’1’ (swap is enabled) the input port and time slot of the CDAx0 is
defined by the TSDP register of CDAx1 and the input port and time slot of CDAx1 is
defined by the TSDP register of CDAx0. The input definition for time slot and data port
CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output
timeslots are not affected by SWAP.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained.
Usually one input and one output of a functional unit (transceiver, HDLC controller, CDA
register) is programmed to a timeslot on IOM
upstream direction the S-transceiver writes data onto IOM
reads data from IOM
programmed as described below under “Monitoring Data”. Besides that none of the
IOM
unit.
Data Sheet
four CDA registers
PCM channels on both data ports (DU, DD). Between reading and writing the data can
be manipulated (processed with an algorithm) by the microcontroller. If this is not the
case a switching function is performed.
â
-2 timeslots must be assigned more than one input and output of any functional
Controller Data Access (CDA)
â
-2). For monitoring data in such cases a CDA register is
Figure
12. The index variables x,y used in the following
â
-2 time slots and more:
30
â
â
-2 (e.g. for B-channel transmission in
-2 interface simultaneously
â
-2 and the U-transceiver
Functional Description
PEF 81902
2001-11-12