sg6742ml Fairchild Semiconductor, sg6742ml Datasheet - Page 9

• Manufacturer Part Number: sg6742ml
• Description: Sg6742ml/mr Highly Integrated Green-mode Pwm Controlle
• Manufacturer: Fairchild Semiconductor

© 2008 Fairchild Semiconductor Corporation
SG6742ML/MR • Rev. 1.0.3
Functional Description
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
R
current drawn from the HV pin is 2.3mA and charges
the hold-up capacitor through the diode and resistor.
When the V
startup current switches off. At this moment, the V
capacitor only supplies the SG6742ML/MR to keep the
V
provides the operating current.
Operating Current
Operating current is around 2.7mA. The low operating
current enables better efficiency and reduces the
requirement of V
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to reduce the switching frequency in light-
load and no-load conditions. The on time is limited for
better abnormal or brownout protection. V
derived from the voltage feedback loop, is taken as the
reference. Once V
switching frequency is continuously decreased to the
minimum green-mode frequency of around 22KHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current-sense signal and V
When the voltage on SENSE pin reaches around
V
immediately. V
voltage around 0.85V for output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 15.5V and 9.5V. During startup, the hold-up capacitor
must be charged to 15.5V through the startup resistor to
enable the IC. The hold-up capacitor continues to
supply V
auxiliary winding of the main transformer. V
drop below 9.5V during startup. This UVLO hysteresis
window ensures that hold-up capacitor is adequate to
supply V
DD
COMP
HV
, (1N4007 / 100KΩ recommended). Typical startup
before the auxiliary winding of the main transformer
=(V
DD
DD
FB
–0.6)/4, the switch cycle is terminated
during startup.
before the energy can be delivered from
DD
COMP
DD
capacitor level reaches V
FB
hold-up capacitance.
is internally clamped to a variable
is lower than the threshold voltage,
FB
, the feedback voltage.
FB
DD
DD-ON
, which is
must not
, the
DD
9
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 5ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability
SG6742ML/MR inserts a synchronized, positive-going,
ramp at every switching cycle.
Constant Output Power Limit
When the SENSE voltage across sense resistor R
reaches the threshold voltage, around 0.9V, the output
GATE drive is turned off after a small delay, t
delay introduces an additional current proportional to t
• V
of the input voltage V
larger additional current and the output power limit is
higher than under low input line voltage. To compensate
this variation for a wide AC input range, a sawtooth
power-limiter is designed to solve the unequal power-
limit problem. The power limiter is designed as a
positive ramp signal fed to the inverting input of the
OCP comparator. This results in a lower current limit at
high-line inputs than at low-line inputs.
V
V
damage due to abnormal conditions. If the V
is over the over-voltage protection voltage (V
lasts for t
the V
again. Over-voltage conditions are usually caused by
open feedback loops.
Thermal Protection
An NTC thermistor, R
be connected from the RT pin to ground. A constant
current I
RT pin can be expressed as V
where I
is smaller, such that V
than 1.05V (V
(t
after 100µs (t
D-OTP1
DD
DD
IN
Over-Voltage Protection (OVP)
/ L
over-voltage protection is built in to prevent
DD
). If V
RT
P
RT
. Since the delay is nearly constant regardless
voltage drops below the UVLO, then starts
D-VDDOVP
is 100µA. At high ambient temperatures, R
and
is output from the RT pin. The voltage on the
RT
D-OTP2
is less than 0.7V (V
RTTH1
prevents
, the PWM pulses are disabled until
).
), the PWM turns off after 12ms
IN
NTC
, higher input voltage results in a
RT
, in series with resistor R
decreases. When V
sub-harmonic
RT=
RTTH2
I
RT
), PWM turns off
• (R
www.fairchildsemi.com
DD-OVP
NTC
oscillation.
DD
RT
PD
voltage
is less
+ R
A
. This
) and
, can
NTC
A
PD
),
S