l99pm62gxp STMicroelectronics, l99pm62gxp Datasheet - Page 69

• Manufacturer Part Number: l99pm62gxp
• Description: Power Management Ic With Lin And High Speed Can
• Manufacturer: STMicroelectronics

L99PM62GXP
6
6.1
6.1.1
6.1.2
ST SPI
SPI communication flow
General description
The proposed SPI communication is based on a standard SPI interface structure using CSN
(Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock)
signal lines.
At device start-up the master reads the <SPI-frame-ID> register (ROM address 3EH) of the
slave device. This 8-bit register indicates the SPI frame length (24bit) and the availability of
additional features.
Each communication frame consists of an instruction byte which is followed by 2 data bytes.
The data returned on SDO within the same frame always starts with the <Global Status>
register. It provides general status information about the device. It is followed by 2 data bytes
(i. e. ‘In-frame-response’).
For write cycles the <Global Status> register is followed by the previous content of the
addressed register.
For read cycles the <Global Status> register is followed by the content of the addressed
register.
A write command is only accepted as a valid command by the device if the counted number
of clocks is exact 24, otherwise the command is rejected.
Command byte
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (<Write>, <Read>, <Read and Clear>, <Read Device
Information>) and a 6 bit address. If less than 6 address bits are required, the remaining bits
are unused but are reserved.
Table 44.
OCx: operating code
Ax: address
Operating code definition
Table 45.
MSB
OC1
OC1
0
0
Op code
Command byte
Operating code definition
OC0
OC0
0
1
A5
Doc ID 17639 Rev 3
A4
A3
Address
<Read Mode>
<Write Mode>
Meaning
A2
A1
LSB
ST SPI
A0
69/102