l99pm62gxp STMicroelectronics, l99pm62gxp Datasheet - Page 97

• Manufacturer Part Number: l99pm62gxp
• Description: Power Management Ic With Lin And High Speed Can
• Manufacturer: STMicroelectronics

L99PM62GXP
Table 104. Status register 3, data bytes
Table 105. Status register 3, bits
Function TSD1 TW
Bit
Group
15
14
13
12
11
10
9
8
7
6
5
4
Device_state
V
V
V
WD_fail_3
WD_fail_2
WD_fail_1
WD_fail_0
1
1
1
_restart_2
_restart_1
_restart_0
V
Name
TSD1
Status register 3
Table 103. Status register 3: command and data bytes
TW
1
_fail
x
state_2
Read/write
Device
1
st
state_1
Device
Thermal warning / shutdown1 occurred since last readout
State from which the device woke up
V
Number of TSD2 events which caused a restart of V
regulator
(7 TSD2 events forces the device into V
Number of missing watchdog triggers
(15 missing watchdog trigger forces the device into V
standby)
data byte <15:8>
1
x
Device state_2
Command byte
fail (V
Diagnosis 5
fail
V
1
1
0
0
1
1
0
restart_2
< 2 V for t > 2 µs) event occurred since last read out
V
1
1
Address
restart_1
0
Doc ID 17639 Rev 3
V
1
Device state_1
0
Comment
restart_0
1
V
1
0
1
0
1
1
fail_3
WD
BAT
fail_2
1
WD
st
Active
V
V
Flash
standby)
Bit <15:8>
Data, 8bit
device woke
1
BAT
data byte
State from
which the
standby
fail_1
WD
standby
up
2
1
nd
BAT
fail_0
WD
data byte <7:0>
Diagnosis 6
Forced
sleep
WD
Bit is latched until a
“read and clear access”
Bit is latched until a
“read and clear access”
after a “read and clear
access”, the device
state is updated
after a wake up, device
state is
01: V
or
10: V
Bit is latched until a
“read and clear access”
Bits are not clearable;
is cleared automatically
if no additional TSD2
event occurs within 1
min.
Bits are not clearable;
is cleared with a proper
Watchdog trigger
Information storage
SHTV1
Forced
TSD2
sleep
2
1
BAT
nd
Data, 8 bit
standby
Bit<7:0>
data byte
standby
state_1
timer
WD
ST SPI
97/102
state_0
timer
WD