l99pm62gxp STMicroelectronics, l99pm62gxp Datasheet - Page 70

• Manufacturer Part Number: l99pm62gxp
• Description: Power Management Ic With Lin And High Speed Can
• Manufacturer: STMicroelectronics

ST SPI
6.1.3
6.1.4
d. See
70/102
Section 6.2
Table 45.
The <Write Mode> <Read Mode> and <Read and Clear Status> operations allow access to
the RAM of the device, i. e. to write to control registers or read status information.
A <Read and Clear Status> operation addressed to a device specific status register reads
back and subsequently clear this status register.
A <Read and Clear Status> operation with address 3FH clears all status registers (including
the Global Status Register). Configuration register is read by this operation.
<Read Device Information> allows access to the ROM area which contains device related
information such as the product family, product name, silicon version, register width and
availability of a watchdog.
More detailed descriptions of the device information are available in ‘Read Device
Information’.
Global status register
Table 46.
Configuration register
The <Configuration> register is accessible at RAM address 3FH.
For the config register, the 8 bits are located in the low byte (LSB).
The configuration register is implemented for compliance purpose to ST SPI standard.
Table 47.
<WD trigger>: this bit is reserved to serve the watchdog.
Global error
flag (GEF)
Bit 7
for details.
Bit 7
0
OC1
1
1
Operating code definition (continued)
Global status register
Configuration register
Bit 6
0
Comm
Bit 6
error
OC0
0
1
Bit 5
OR comm error)
0
Not (chip reset
(d)
Bit 5
Doc ID 17639 Rev 3
Bit 4
0
TSD2
Bit 4
Bit 3
0
<Read Device Information>
<Read and Clear Status>
Bit 2
TSD1
0
Bit 3
Meaning
Bit 1
V
0
Bit 2
1
Fail
(OV/UV)
VS Fail
Bit 1
WD trigger
L99PM62GXP
Bit 0
Bit 0
safe
Fail