ml4824cs-2 Fairchild Semiconductor, ml4824cs-2 Datasheet - Page 10

• Manufacturer Part Number: ml4824cs-2
• Description: Power Factor Correction And Pwm Controller Combo
• Manufacturer: Fairchild Semiconductor

ML4824
FUNCTIONAL DESCRIPTION
No voltage error amplifier is included in the PWM stage
of the ML4824, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
allows V
input voltages below 1.25V.
PWM Current Limit
The DC I
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the
clock pulse at the start of the next PWM power cycle.
V
The V
and inhibits the PWM if this voltage on V
nominal 2.5V. Once this voltage reaches 2.5V, which
corresponds to the PFC output capacitor being charged to
its rated boost voltage, the soft-start begins.
PWM Control (RAMP 2)
When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
timing components (R
minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed
by the following equation:
where C
t
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
10
DELAY
IN
OK Comparator
C
IN
SS
is the desired start-up delay.
OK comparator monitors the DC output of the PFC
SS
DC
LIMIT
t
is the required soft start capacitance, and
DELAY
to command a zero percent duty cycle for
pin is a direct input to the cycle-by-cycle
50
125
.
RAMP2
V
A
, C
RAMP2
), which will have a
FB
(Continued)
is less than its
(6)
Solving for the minimum value of C
Caution should be exercised when using this minimum
soft start capacitance value because premature charging
of the SS capacitor and activation of the PWM section
can result if V
comparator at start-up. The magnitude of V
related both to line voltage and nominal PFC output
voltage. Typically, a 1.0 F soft start capacitor will allow
time for V
prior to activation of the PWM section at line voltages
between 90Vrms and 265Vrms.
Generating V
The ML4824 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the voltage
internal to the part at 13.5V. This allows a low power
dissipation while at the same time delivering 10V of gate
drive at the PWM OUT and PFC OUT outputs. It is
important to limit the current through the part to avoid
overheating or destroying it. This can be easily done with a
single resistor in series with the Vcc pin, returned to a bias
supply of typically 18V to 20V. The resistor’s value must be
chosen to meet the operating current requirement of the
ML4824 itself (19mA max) plus the current required by the
two gate driver outputs.
EXAMPLE:
With a V
ML4824 driving a total gate charge of 110nC at 100kHz
(e.g., 1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate
driver current required is:
To check the maximum dissipation in the ML4824, find
the current at the minimum V
The maximum allowable I
acceptable design.
The ML4824 should be locally bypassed with a 10nF and
a 1 F ceramic capacitor. In most applications, an
electrolytic capacitor of between 100 F and 330 F is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.
I
R
I
C
GATEDRIVE
CC
BIAS
SS
BIAS
FB
20
5
ms
19
and PFC out to reach their nominal values
20
V
of 20V, a V
CC
180
FB
mA
V
100
is in the hysteresis band of the V
50
125
12 4
.
.
14 6
11
kHz
A
V
V
.
mA
V
CC
200
42 2
CC
limit of 14.6V (max) and the
100
.
180
nF
CC
is 55mA, so this is an
mA
nC
(12.4V):
11
SS
mA
:
REV. 1.01 12/7/2000
FB
at start-up is
IN
OK
(7)
(8)
(9)