tc9444f TOSHIBA Semiconductor CORPORATION, tc9444f Datasheet - Page 20

• Manufacturer Part Number: tc9444f
• Description: Single-chip Karaoke Ic Ii
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note 15: At a reset, the initial values are SYNM2 = SYNM1 = 0, RLS = 1, D0 = 00H.
4. AD Converter
5. DA Converter
CH
D
3.18 MODE Command
oversampling rate. The AD converter performs three-channel interleave processing for the line input
L/R-channels and the microphone input.
the microphone echo signal are combined outside the IC. The microphone main signal and the microphone
echo component can also be added internally using a microphone through-path in the IC.
AIR-LPFO3 pins.
The TC9444F incorporates a successive approximation 6-bit AD converter with a two times
The microphone input is designed to internally generate an echo effect. The microphone main signal and
When not using an AD converter, connect jumpers between the MICI-LPFO, AIL-LPFO2, and
Incorporates a SD -type modulation -bit DA converter and a tertiary analog post filter.
(master mode, 16-bit input/output)
SYNM1, 2: Select sync mode
RLS: Selects the channel clock polarity (when RLS = “H” and LRCK = “L” or when RLS = “L” and LRCK =
OBIT1, 2: Select the digital audio output format.
IBIT1, 2, 3: Select the digital audio input format.
MCKINH: When “H”, disables the MCKO pin output (MCK pin is fixed to low).
DZINH: When “H”, disables the digital zero detection output (DZ pin is fixed to low).
ADPD: When “H”, the AD converter power save and output are masked by setting them to digital zeros.
MCKO pin. The MCKO pin uses a large output buffer for high-speed clock output. However, to
suppress unnecessary output without using this pin, set MCKINH to High.
from the SDI pin are all zeroes and by setting the DZ pin high if all-zero input continues for a
specified detection time (Table 2.4).
setting the DZ pin to High. The DZINH bit is used to inhibit the DZ pin from going High.
output by setting to digital zeros. As some circuitry is halted at this time, the power dissipation drops
slightly.
3
0
Command to set the IC operating mode by adding one-byte data.
This command bundles parameters so that they need be set once only at power-on.
The CL bits are also used to make settings.
The MCKINH bit is used to halt the XI input clock (or the halved input clock) output from the
A function is supported to forcibly mute the DAC output by checking whether digital data input
When digital input and analog input are switched, digital input zero detection becomes active,
Setting the ADPD bit to High halts the AD converter internal circuits and masks the AD converter
“H”, L-channel data selected).
SYMM2
2
CL
SYMM1
1
Table 3.23 MODE Command
RLS
0
OBIT2
7
20
OBIT1
6
IBIT3
5
IBIT2
4
D0
IBIT1
3
MCKINH
2
DZINH
2002-01-11
TC9444F
1
ADPD
0