attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 131

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

12.11.9
12.11.10 Timer/Counter1 Interrupt Flag Register – TIFR1
7728A–AUTO–07/08
Timer/Counter1 Interrupt Mask Register – TIMSK1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICIE1: Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
located in TIFR1, is set.
• Bit 4..3 – Reserved Bits
These bits are reserved for future use.
• Bit 2 – OCIE1B: Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
flag, located in TIFR1, is set.
• Bit 1 – OCIE1A: Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
flag, located in TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See ”Interrupt Vectors in ATtiny167” on page
TIFR1, is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See ”Interrupt Vectors in ATtiny167” on page
See Section “12.3” on page 106.
(See ”Interrupt Vectors in ATtiny167” on page
(See ”Interrupt Vectors in ATtiny167” on page
R
R
7
–
0
7
–
0
6
–
R
0
R
6
–
0
ICIE
ICF
R/W
R/W
5
0
5
0
1
1
R
4
–
0
R
4
–
0
57.) is executed when the TOV1 flag, located in
R
3
–
0
R
3
–
0
57.) is executed when the ICF1 flag,
OCIE
OCF
R/W
R/W
57.) is executed when the OCF1B
57.) is executed when the OCF1A
2
0
2
0
1
1
B
B
OCIE
OCF
R/W
R/W
1
0
1
0
1
1
A
A
ATtiny167
TOIE
TOV
R/W
R/W
0
0
0
0
1
1
TIFR
TIMSK
1
1
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