attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 201
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attiny167-esxz
Manufacturer Part Number
attiny167-esxz
Description
8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
Manufacturer
ATMEL Corporation
Datasheet
1.ATTINY167-ESXZ.pdf
(277 pages)
- Current page: 201 of 277
- Download datasheet (4Mb)
17.11.6
17.11.7
7728A–AUTO–07/08
DIDR1 – Digital Input Disable Register 1
AMISCR – Analog Miscellaneous Control Register
• Bits 7:3 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be written
to zero when DIDR1 is written.
• Bits 2..0 – ADC10D..ADC8D: ADC10..8 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC10:8 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
• Bits 7:3 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be written
to zero when AMISCR is written.
• Bit 2 – AREFEN: External Voltage Reference Input Enable
When this bit is written logic one, the voltage reference for the ADC is input from AREF pin as
described in
AREF higher than (AVcc - 1V) is not recommended, as this will affect ADC accuracy. The inter-
nal voltage reference options may not be used if an external voltage is being applied to the
AREF pin. It is recommended to use DIDR register bit function (digital input disable) when
AREFEN is set.
• Bit 1 – XREFEN: Internal Voltage Reference Output Enable
When this bit is written logic one, the internal voltage reference 1.1V or 2.56V is output on XREF
pin as described in
tion (digital input disable) when XREFEN is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Table 17.10 on page
R
R
7
0
7
0
-
-
Table 17.10 on page
R
R
6
0
6
0
-
-
194. If active channels are used, using AVcc or an external
R
R
5
0
5
0
-
-
194. It is recommended to use DIDR register bit func-
R
R
4
0
4
0
-
-
R
R
3
0
3
0
-
-
ADC10D
AREFEN
R/W
R/W
2
0
2
0
XREFEN
ADC9D
R/W
R/W
1
0
1
0
ATtiny167
ISRCEN
ADC8D
R/W
R/W
0
0
0
0
AMISCR
DIDR1
201
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