attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 39
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attiny167-esxz
Manufacturer Part Number
attiny167-esxz
Description
8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
Manufacturer
ATMEL Corporation
Datasheet
1.ATTINY167-ESXZ.pdf
(277 pages)
- Current page: 39 of 277
- Download datasheet (4Mb)
4.5.4
7728A–AUTO–07/08
CLKSELR - Clock Selection Register
• Bits 3:0 – CLKC3:0: Clock Control Bits 3 - 0
These bits define the command to provide to the ‘Clock Switch’ module. The special write proce-
dure must be followed to change the CLKC3..0 bits
Change Enable” on page
1. Write the Clock Control Change Enable (CLKCCE) bit to one and all other bits in
2. Within 4 cycles, write the desired value to CLKCSR register while clearing CLKCCE bit.
Interrupts should be disabled when setting CLKCSR register in order not to disturb the
procedure.
Table 4-11.
• Bit 7– Res: Reserved Bit
This bit is reserved bit in the ATtiny167 and will always read as zero.
• Bit 6 – COUT: Clock Out
The COUT bit is initialized with ~(CKOUT) Fuse bit.
The COUT bit is only used in case of ‘CKOUT’ command. Refer to
Buffer” on page 30
In case of ‘Recover System Clock Source’ command, COUT it is not affected (no recovering of
this setting).
• Bits 5:4 – CSUT1:0: Clock Start-up Time
CSUT bits are initialized with the values of SUT Fuse bits.
In case of ‘Enable/Disable Clock Source’ command, CSUT field provides the code of the clock
start-up time. Refer to subdivisions of
start-up times.
Bit
Read/Write
Initial Value
Clock Command
No command
Disable clock source
Enable clock source
Request for clock
Clock source switch
Recover system clock source code
Enable watchdog in automatic reload mode
CKOUT command
No command
CLKCSR to zero.
Clock command list.
R
7
0
-
availability
for using.
~ (CKOUT)
COUT
R/W
fuse
38.).
6
CSUT1
R/W
5
SUT1..0
Section 4.2 ”Clock Sources” on page 24
fuses
CSUT0
R/W
4
CSEL3
R/W
3
(See ”Bit 7 – CLKCCE: Clock Control
CSEL2
R/W
2
CKSEL3..0
CLKC3..0
fuses
1xxx
0000
0001
0010
0011
0100
0101
0110
0111
Section 4.2.7 ”Clock Output
CSEL1
R/W
b
b
b
b
b
b
b
b
b
1
ATtiny167
CSEL0
for code of clock
R/W
0
CLKSELR
39
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