attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 51

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

6.2
6.2.1
6.3
6.3.1
7728A–AUTO–07/08
Internal Voltage Reference
Watchdog Timer
Voltage Reference Enable Signals and Start-up Time
Watchdog Timer Behavior
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
Reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the Reset Flags.
ATtiny167 features an internal bandgap reference. This reference is used for Brown-out Detec-
tion, and it can be used as an input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACIRS bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode or in Power-save, the user
can avoid the three conditions above to ensure that the reference is turned off before entering in
these power reduction modes.
ATtiny167 has an Enhanced Watchdog Timer (WDT). The main features are:
•
•
•
•
The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 KHz oscillator.
Clocked from separate On-chip Oscillator
4 Operating modes
Selectable Time-out period from 16ms to 8s
Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
ACIRS bit in ACSR).
– Interrupt
– System Reset
– Interrupt and System Reset
– Clock Monitoring
Table 22-7 on page
237. To save power, the reference is not always
ATtiny167
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