attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 55

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

6.3.3
7728A–AUTO–07/08
Watchdog Timer Control Register - WDTCR
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in
SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is
enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt
Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE
and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is
useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a
System Reset will be applied.
If the Watchdog Timer is used as clock monitor (c.f.
Bits 3 - 0” on page
cally disabled.
Table 6-1.
Note:
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
Bit
Read/Write
Initial Value
Monitor
Clock
On
Off
x
1. At least one of these three enables (WDTON, WDE & WDIE) equal to 1.
WDTON
Watchdog Timer Configuration
WDIF
R/W
y
0
0
0
0
1
7
0
(1)
39), the System Reset Mode is enabled and the Interrupt Mode is automati-
WDE
WDIE
R/W
y
0
0
1
1
x
6
0
(1)
WDIE
y
WDP3
0
1
0
1
x
(1)
R/W
5
0
Mode
Stopped
System Reset Mode
Interrupt Mode
System Reset Mode
Interrupt and System Reset
Mode
System Reset Mode
WDCE
R/W
4
0
Section • ”Bits 3:0 – CLKC3:0: Clock Control
WDE
R/W
3
X
WDP2
R/W
2
0
Action on Time-out
None
Reset
Interrupt
Reset
Interrupt, then go to System
Reset Mode
Reset
WDP1
R/W
1
0
ATtiny167
WDP0
R/W
0
0
WDTCR
55