p87c770aar NXP Semiconductors, p87c770aar Datasheet - Page 51

• Manufacturer Part Number: p87c770aar
• Description: Microcontrollers Ntsc With On-screen Display Closed Caption
• Manufacturer: NXP Semiconductors

Philips Semiconductors
18.8
18.8.1
The horizontal and vertical input sync signals can be
inverted by setting the HPOL and VPOL bits in the Text
Vertical Position Register (see Section 18.9.2).
Table 74 Sync signal polarity
18.8.2
Normally, VSYNC of the first field occurs during the first
half line period and Vsync of the second field occurs during
the second half period of a scan-line. In this case it is very
easy to generate a frame reset signal. The VSYNC pulse
is generated by sampling and rising edge detection.
1999 Jun 11
handbook, full pagewidth
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
HPOL
0
1
(sampled)
(sampled)
Vsync_In
Vsync_In
Vsync
Vsync
General controls
Frame
Field 1
Field 2
Frame
Hsync
Hsync
reset
reset
P
F
H50
H50
RAME RESET GENERATION
OLARITY OF
VPOL
0
1
HSYNC
input polarity
input inverted polarity
SYNC SIGNAL POLARITY
AND
VSYNC
INPUT SIGNALS
Fig.22 Frame reset timing.
51
These VSYNC pulses are gated (AND gate) with a line
frequency signal which has a duty cycle of 50 : 50 (H50).
The output signal is the frame reset pulse. The rising edge
of the H50 signal is generated from the HSYNC pulse.
The falling edge is generated via a comparison between
the fixed value of half of the nominal number of 768 pixels
per line (comparator value: 384 pixels) and the value of a
pixel counter.
If the VSYNC of one field occurs shortly after the falling
edge of H50 and the line period has more than the nominal
number of 768 pixels per line, it is possible that both
VSYNC pulses occur during the low period of H50.
The result is that no frame reset pulse is generated. In the
case of a VSYNC pulse occurring shortly after the rising
edge of H50 and less than the nominal number of
768 pixels per line it is possible that every VSYNC pulse
will generate a frame reset pulse. To prevent this
happening the position of H50 is adjustable in increments
of 12 clock cycles. The adjustment value is selected using
the Odd/Even Align Register.
P8xCx70 family
Product specification
MGL151