lpc2470fet208 NXP Semiconductors, lpc2470fet208 Datasheet - Page 25

• Manufacturer Part Number: lpc2470fet208
• Description: Flashless 16-bit/32-bit Micro; Ethernet, Can, Lcd, Usb 2.0 Device/host/otg, External Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[7]
[8]
[9]
[10] Pad provides special analog functionality.
[11] Pad provides special analog functionality.
[12] Pad provides special analog functionality.
[13] Pad provides special analog functionality.
[14] Pad provides special analog functionality.
[15] Either the I
[16] Either the USB OTG function or the LCD function is selectable, see
[17] Either the trace function or the LCD function is selectable, see
[18] Either one of the external interrupts EINT1 to EINT3 or the LCD function is selectable, see
[19] Either one of the timer outputs MAT2[1] and MAT2[0] or the LCD function is selectable, see
7. Functional description
LPC2470_0
Preliminary data sheet
5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
Pad provides special analog functionality.
Pad provides special analog functionality.
2
S function or the LCD function is selectable, see
7.1 Architectural overview
The LPC2470 microcontroller consists of an ARM7TDMI-S CPU with emulation support,
the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip
memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external
memory, and the AMBA APB for connection to other on-chip peripheral functions. The
microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte
order.
The LPC2470 implements two AHB buses in order to allow the Ethernet block to operate
without interference caused by other system activity. The primary AHB, referred to as
AHB1, includes the VIC, GPDMA controller, and EMC.
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,
and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2
are the ARM7 and the Ethernet block.
AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB
ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the
AHB address space. Lower speed peripheral functions are connected to the APB bus.
The AHB to APB bridge interfaces the APB bus to the AHB bus. APB peripherals are also
allocated a 2 MB range of addresses, beginning at the 3.5 GB address point. Each APB
peripheral is allocated a 16 kB address space within the APB address space.
The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers
high performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed complex
instruction set computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Rev. 00.01 — 5 October 2007
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11,
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Fast communication chip
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12, and
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LPC2470
© NXP B.V. 2007. All rights reserved.
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