lpc2470fet208 NXP Semiconductors, lpc2470fet208 Datasheet - Page 56
lpc2470fet208
Manufacturer Part Number
lpc2470fet208
Description
Flashless 16-bit/32-bit Micro; Ethernet, Can, Lcd, Usb 2.0 Device/host/otg, External Memory Interface
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2470FET208.pdf
(72 pages)
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LPC2470_0
Preliminary data sheet
Fig 7. External clock timing
Fig 8. Differential data-to-EOP transition skew and EOP width
Fig 9. MISO line set-up time in SSP Master mode
t
PERIOD
differential
data lines
10.1 Timing
MOSI
MISO
shifting edges
SCK
V
DD
− 0.5 V
0.45 V
0.2V
0.2V
n × t
DD
differential data to
crossover point
SE0/EOP skew
DD
PERIOD
− 0.1 V
+ 0.9 V
+ t
FDEOP
Rev. 00.01 — 5 October 2007
t
t
CHCL
su(SPI_MISO)
crossover point
t
CLCX
extended
T
cy(clk)
t
CLCH
t
CHCX
sampling edges
source EOP width: t
receiver EOP width: t
Fast communication chip
002aaa907
002aad326
LPC2470
© NXP B.V. 2007. All rights reserved.
FEOPT
002aab561
EOPR1
, t
EOPR2
56 of 72
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