mc9s08jm60 Freescale Semiconductor, Inc, mc9s08jm60 Datasheet - Page 17

• Manufacturer Part Number: mc9s08jm60
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

17.3 Register Definition ........................................................................................................................298
17.4 Functional Description ..................................................................................................................309
18.1 Introduction ...................................................................................................................................325
18.2 Background Debug Controller (BDC) ..........................................................................................326
18.3 On-Chip Debug System (DBG) ....................................................................................................335
18.4 Register Definition ........................................................................................................................339
Freescale Semiconductor
17.2.3 V
17.3.1 USB Control Register 0 (USBCTL0) .............................................................................299
17.3.2 Peripheral ID Register (PERID) .....................................................................................299
17.3.3 Peripheral ID Complement Register (IDCOMP) ............................................................300
17.3.4 Peripheral Revision Register (REV) ...............................................................................300
17.3.5 Interrupt Status Register (INTSTAT) ..............................................................................301
17.3.6 Interrupt Enable Register (INTENB) ..............................................................................302
17.3.7 Error Interrupt Status Register (ERRSTAT) ...................................................................303
17.3.8 Error Interrupt Enable Register (ERRENB) ...................................................................304
17.3.9 Status Register (STAT) ....................................................................................................305
17.3.10 Control Register (CTL) ..................................................................................................306
17.3.11 Address Register (ADDR) .............................................................................................307
17.3.12 Frame Number Register (FRMNUML, FRMNUMH) ..................................................307
17.3.13 Endpoint Control Register (EPCTLn, n=0-6) ................................................................308
17.4.1 Block Descriptions ..........................................................................................................309
17.4.2 Buffer Descriptor Table (BDT) .......................................................................................314
17.4.3 USB Transactions ...........................................................................................................317
17.4.4 USB Packet Processing ...................................................................................................319
17.4.5 Start of Frame Processing ...............................................................................................320
17.4.6 Suspend/Resume .............................................................................................................321
17.4.7 Resets ..............................................................................................................................322
17.4.8 Interrupts .........................................................................................................................323
18.1.1 Features ...........................................................................................................................326
18.2.1 BKGD Pin Description ...................................................................................................327
18.2.2 Communication Details ..................................................................................................328
18.2.3 BDC Commands .............................................................................................................332
18.2.4 BDC Hardware Breakpoint .............................................................................................334
18.3.1 Comparators A and B .....................................................................................................335
18.3.2 Bus Capture Information and FIFO Operation ...............................................................335
18.3.3 Change-of-Flow Information ..........................................................................................336
18.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................336
18.3.5 Trigger Modes .................................................................................................................337
18.3.6 Hardware Breakpoints ....................................................................................................339
18.4.1 BDC Registers and Control Bits .....................................................................................339
18.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................341
18.4.3 DBG Registers and Control Bits .....................................................................................342
USB33 ............................................................................................................................................................. 298
MC9S08JM60 Series Data Sheet, Rev. 2
Development Support
Chapter 18
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