mc9s08jm60 Freescale Semiconductor, Inc, mc9s08jm60 Datasheet - Page 190

• Manufacturer Part Number: mc9s08jm60
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Multi-Purpose Clock Generator (S08MCGV1)
12.4
12.4.1
The nine states of the MCG are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
12.4.1.1
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
190
IREFS=1
CLKS=01
BDM Disabled
and LP=1
•
•
•
•
CLKS bits are written to 00
IREFS bit is written to 1
PLLS bit is written to 0
RDIV bits are written to 000. Since the internal reference clock frequency should already be in the
range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary.
Functional Description
Operational Modes
FLL Engaged Internal (FEI)
Internal (BLPI)
Low Power
Entered from any state
when MCU enters stop
Bypassed
BDM Enabled
or LP=0
IREFS=1
CLKS=00
PLLS=0
IREFS=1
CLKS=01
PLLS=0
Figure 12-8. Clock Switching Modes
FLL Engaged
Internal (FEI)
MC9S08JM60 Series Data Sheet, Rev. 2
FLL Bypassed
Internal (FBI)
Stop
FLL Engaged
External (FEE)
PLL Bypassed
External (PBE)
FLL Bypassed
External (FBE)
PLL Engaged
External (PEE)
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
IREFS=0
CLKS=00
PLLS=0
BDM Enabled
or LP=0
BDM Enabled
or LP=0
IREFS=0
CLKS=10
PLLS=0
IREFS=0
CLKS=10
PLLS=1
IREFS=0
CLKS=00
PLLS=1
External (BLPE)
Low Power
Bypassed
Freescale Semiconductor
IREFS=0
CLKS=10
BDM Disabled
and LP=1