km4132g271b Samsung Semiconductor, Inc., km4132g271b Datasheet - Page 18

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km4132g271b

Manufacturer Part Number
km4132g271b
Description
128k X 32bit X 2 Banks Synchronous Graphic Ram Lvttl
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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KM4132G271B
SUMMARY OF 1M Byte SGRAM BASIC FEATURES AND BENEFITS
Interface
Bank
Page Depth / 1 Row
Total Page Depth
Burst Length(Read)
Burst Length(Write)
Burst Type
CAS Latency
Block Write
Color Register
Mask Register
Mask function
Features
Pixel Mask at Block Write
Sequential & Interleave
128K x 32 x 2 SGRAM
1, 2, 4, 8 Full Page
1, 2, 4, 8 Full Page
Synchronous
Write per bit
1024 bytes
8 Columns
DQM
256 bit
BRSW
1 ea.
1 ea.
2 ea
2, 3
0-3
Better interaction between memory and system without wait-state of
asynchronous DRAM.
High speed vertical and horizontal drawing.
High operating frequency allows performance gain for SCROLL, FILL,
and BitBLT.
Pseudo-infinite row length by on-chip interleaving operation.
Hidden row activation and precharge.
High speed vertical and horizontal drawing.
High speed vertical and horizontal drawing.
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
Switch to burst length of 1 at write without MRS.
Compatible with Intel and Motorola CPU based system.
Programmable CAS latency.
High speed FILL, CLEAR, Text with color registers.
Maximum 32 byte data transfers(e.g. for 8bpp : 32 pixels) with plane and
byte masking functions.
A and B bank share.
Write-per-bit capability(bit plane masking). A and B banks share.
Byte masking(pixel masking for 8bpp system) for data-out/in
Each bit of the mask register directly controls a corresponding bit plane.
Byte masking(pixel masking for 8bpp system) for color by DQi
- 18
Benefits
Rev. 2.4 (May 1998)
CMOS SGRAM

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