km4132g271b Samsung Semiconductor, Inc., km4132g271b Datasheet - Page 50

• Manufacturer Part Number: km4132g271b
• Description: 128k X 32bit X 2 Banks Synchronous Graphic Ram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

KM4132G271B
FUNCTION TRUTH TABLE (TABLE 1, Continued)
FUNCTION TRUTH TABLE for CKE(TABLE 2)
Precharge
other than
*Note :
Any State
*Note :
ABBREVIATIONS
Current
ABBREVIATIONS : ABI = All Banks Idle
Refresh
Power
Banks
Above
Down
Listed
State
Bank
Both
Self
Idle
All
1. All entries assume that CKE was active(High) during the preceding clock cycle and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA(and PA).
5. Illegal if any banks is not idle.
6. Legal only if all banks are in idle or row active state.
7. After CKE s low to high transition to exist self refresh mode. And a time of
8. CKE low to high transition is asynchronous as if restarts internal clock.
9. Power-down and self refresh can be entered only from the all banks idle state.
10. Must be a legal command.
RA = Row Address(A
NOP = No Operation Command
transition to issue a new command.
A minimum setup time "
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CKE
X
H
H
H
H
H
X
H
H
H
H
H
H
H
H
n
L
L
L
L
L
L
L
L
L
L
L
L
L
0
~A
CS
X
H
X
X
H
X
X
H
X
X
X
X
X
9
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
t
)
SS
+ one clock" must be satisfied before any command other than exit.
RAS
X
X
H
H
H
X
X
X
H
H
H
X
X
X
H
H
H
X
X
X
X
X
L
L
L
L
L
L
BA = Bank Address(A
CA = Column Address(A
CAS
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
WE
X
X
H
X
X
X
X
X
H
X
X
X
X
X
H
X
H
H
X
X
X
X
X
L
L
L
L
L
DSF
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
L
L
- 50
10
0
)
~A
7
)
OP Code
OP Code
ADDR
RA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
t
RC
PA = Precharge All(A
AP = Auto Precharge(A
(min) has to be elapse after CKE s low to high
INVALID
Exit Self Refresh --> ABI after
Exit Self Refresh --> ABI after
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Self Refresh)
INVALID
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Power Down Mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
Enter Self Refresh
Mode Register Access
Special Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain clock Suspend
9
)
ACTION
9
)
Rev. 2.4 (May 1998)
CMOS SGRAM
t
t
RC
RC
NOTE
10
10
7
7
8
8
9
9
9