km4132g271b Samsung Semiconductor, Inc., km4132g271b Datasheet - Page 25

• Manufacturer Part Number: km4132g271b
• Description: 128k X 32bit X 2 Banks Synchronous Graphic Ram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

KM4132G271B
12. About Burst Type Control
13. About Burst Length Control
Random
Random
Pseudo-
Interrupt
Special
MODE
MODE
MODE
MODE
MODE
MODE
MODE
Basic
Basic
(Interrupted by Precharge)
Random column Access
Decrement Sequential
Sequential Counting
Interleave Counting
Binary Counting
RAS Interrupt
CAS Interrupt
Block Write
t
CCD
Burst Stop
Full Page
Counting
Pseudo-
Pseudo-
BRSW
= 1 CLK
1
2
4
8
At MRS A
At auto precharge, t
At MRS A
At auto precharge, t
At MRS A
At MRS A
At MRS A
Wrap around mode(Infinite burst length)should be stopped by burst stop,
RAS interrupt or CAS interrupt.
At MRS A
Read burst =1, 2, 4, 8, full page/write Burst =1
At auto precharge of write, t
8 Column Block Write. LSB A0-2 are ignored. Burst length=1.
At auto precharge, t
Using burst stop command, it is possible only at full page burst length.
Before the end of burst, Row precharge command of the same bank
stops read/write burst with Row precharge.
t
During read/write burst with auto precharge, RAS interrupt cannot be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
During read/write burst with auto precharge, CAS interrupt can not be issued.
At MRS A
BL=1, 2, 4, 8 and full page wrap around.
At MRS A
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
At MRS A
Starting Address LSB 3 bits A
-- if LSB="000" : Increment Counting.
-- if LSB="111" : Decrement Counting.
For Example,(Assume Addresses except LSB 3 bits are all 0, BL=8)
-- @ write, LSB="000", Accessed Column in order 0-1-2-3-4-5-6-7
-- @ read, LSB="111", Accessed Column in order 7-6-5-4-3-2-1-0
At BL=4, same applications are possible. As above example, at Interleave Counting mode,
by confining starting address to some values, Pseudo-Decrement Counting Mode can be
realized. See the BURST SEQUENCE TABLE carefully.
At MRS A
Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be realized.
-- @ Sequential Counting, Accessed Column in order 3-4-5-6-7-1-2-3(BL=8)
-- @ Pseudo-Binary Counting,
Accessed Column in order 3-4-5-6-7-8-9-10(Burst Stop command)
Note. The next column address of 256 is 0.
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
t
t
RDL
BWC
BDL
= 1 with DQM, valid DQ after burst stop is 1, 2 for CL= 2, 3 respectively
= 1, Valid DQ after burst stop is 1, 2 for CL=2, 3 respectively
should not be violated.
A
2,1,0
2,1,0
2,1,0
2,1,0
2,1,0
9
0-2
3
3
3
3
= "1".
= "0". See the BURST SEQUENCE TABLE. (BL=4,8)
= "1". See the BURST SEQUENCE TABLE. (BL=4,8)
= "1".(See to Interleave Counting Mode)
= "0".(See to Sequential Counting Mode)
= "111".(See to Full Page Mode)
= "111".
= "000".
= "001".
= "010".
= "011".
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RAS
RAS
RAS
should not be violated.
should not be violated.
should not be violated.
RAS
0-2
should not be violated.
should be "000" or "111".@BL=8.
Rev. 2.4 (May 1998)
CMOS SGRAM