tc59lm818dmb TOSHIBA Semiconductor CORPORATION, tc59lm818dmb Datasheet

tc59lm818dmb

Manufacturer Part Number

tc59lm818dmb

Description

288mbits Network Fcram2 ? 4,194,304-words ? 4 Banks ? 18-bits

Manufacturer

TOSHIBA Semiconductor CORPORATION

Datasheet

1.TC59LM818DMB.pdf (57 pages)

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BOSTOCK HK LIMITED

Part Number:

tc59lm818dmb-33

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TOSHIBA-Pb

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TENTATIVE

288Mbits Network FCRAM2

− 4,194,304-WORDS × 4 BANKS × 18-BITS

DESCRIPTION

FCRAM

bits. TC59LM818DMB feature a fully synchronous operation referenced to clock edge whereby all operations are

synchronized at a clock input which enables high performance and simple user interface coexistence.

TC59LM818DMB can operate fast core cycle compared with regular DDR SDRAM.

power consumption are required. The Output Driver for Network FCRAM

transfer under light loading condition.

FEATURES

•

Notice: FCRAM is trademark of Fujitsu limited, Japan.

Network FCRAM

TC59LM818DMB is suitable for Network, Server and other applications where large memory density and low

•

Fast clock cycle time of 3.33 ns minimum

Quad Independent Banks operation

Fast cycle and Short Latency

Selectable Data Strobe

Distributed Auto-Refresh cycle in 3.9 µs

Self-Refresh

Power Down Mode

Variable Write Length Control

Write Latency = CAS Latency-1

Programable CAS Latency and Burst Length

Organization: 4,194,304 words × 4 banks × 18 bits

Power Supply Voltage

Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL

Package:

DD2P

DD6

RAC

DD1S

Fully Synchronous Operation

Double Data Rate (DDR)

Data input/output are synchronized with both edges of DS / QS.

Differential Clock (CLK and CLK ) inputs

Output data (DQs and QS) is aligned to the crossings of CLK and CLK .

Clock:

Data:

Burst Length = 2, 4

CS , FN and all address input signals are sampled on the positive edge of CLK.

CAS Latency = 4, 5, 6

Clock Cycle Time (min)

Random Read/Write Cycle Time (min)

Random Access Time (max)

Operating Current (single bank) (max)

Power Down Current (max)

Self-Refresh Current (max)

containing 301,989,888 memory cells. TC59LM818DMB is organized as 4,194,304-words × 4 banks × 18

300 MHz maximum

600 Mbps/pin maximum

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

60Ball BGA, 1mm × 1mm Ball pitch (P-BGA60-0917-1.00AZ)

PARAMETER

is Double Data Rate Fast Cycle Random Access Memory. TC59LM818DMB is Network

DDQ

: 1.4 V ~ 1.9 V

2.5 V ± 0.125V

CL = 4

CL = 5

CL = 6

235 mA

3.75 ns

3.33 ns

22.5 ns

65 mA

15 mA

4.5 ns

-33

TC59LM818DMB

210 mA

60 mA

15 mA

5.0 ns

4.5 ns

4.0 ns

25 ns

TC59LM818DMB-33,-40

-40

is capable of high quality fast data

2005-10-19 1/57

Rev 1.4

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