tc59lm818dmb TOSHIBA Semiconductor CORPORATION, tc59lm818dmb Datasheet - Page 40
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tc59lm818dmb
Manufacturer Part Number
tc59lm818dmb
Description
288mbits Network Fcram2 ? 4,194,304-words ? 4 Banks ? 18-bits
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TC59LM818DMB.pdf
(57 pages)
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Unidirectional DS/Free Running QS mode
Unidirectional DS/QS mode
Command
Address
(output)
(output)
(output)
(output)
POWER DOWN TIMING (CL = 4, BL = 4)
(input)
(input)
Read cycle to Power Down Mode
CLK
PD
CLK
DQ
DQ
DS
QS
DS
QS
Note: PD must be kept "High" level until end of Burst data output.
RDA
UA
0
Low
Hi-Z
Hi-Z
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied l
PD should be brought to "High" within t
LAL
LA
1
2
CL = 4
CL = 4
3
4
5
Q0 Q1
Q0 Q1
DESL
REFI
t
6
QPDH
Q2 Q3
Q2 Q3
(max.) to maintain the data written into cell.
t
IH
Power Down Entry
7
t
IS
8
I
PD
= 2 cycle
9
l
RC(min)
10
TC59LM818DMB-33,-40
, t
REFI(max)
n-2
PDA
cycles later.
n-1
2005-10-19 40/57
Power Down Exit
n
Hi-Z
Hi-Z
DESL
n+1
Rev 1.4
I
t
PDA
PDEX
n+2
WRA
RDA
UA
or
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