tc59lm906amg TOSHIBA Semiconductor CORPORATION, tc59lm906amg Datasheet
tc59lm906amg
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tc59lm906amg Summary of contents
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... Random Access Memory (Network FCRAM as 4,194,304-words 8 banks 16 bits, TC59LM906AMG is organized as 8,388,608-words TC59LM914/06AMG feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM914/06AMG can operate fast core cycle compared with regular DDR SDRAM. ...
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... TC59LM906AMG PIN NAMES PIN NAME A0~A13 Address Input BA0~BA2 Bank Address DQ0~DQ7 Data Input / Output CS Chip Select FN Function Control PD Power Down Control CLK, CLK Clock Input 4 bank operation can be performed using BA2 as A14. PIN ASSIGNMENT (TOP VIEW) ball pitch=1.0 x 1.0mm ...
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TC59LM914AMG PIN NAMES PIN NAME A0~A13 Address Input BA0~BA2 Bank Address DQ0~DQ15 Data Input / Output CS Chip Select FN Function Control PD Power Down Control CLK, CLK Clock Input 4 bank operation can be performed using BA2 as A14. ...
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... LOWER ADDRESS LATCH REFRESH COUNTER BURST COUNTER Note: The TC59LM906AMG configuration is 8 Banks of 16384 The TC59LM914AMG configuration is 8 Banks of 16384 TC59LM906AMG has DQS, DQS pin for Differential Data Strobe. TC59LM914AMG has UDQS and LDQS. TC59LM914/06AMG-37,-50 To each block BANK #2 BANK #1 BANK #0 MEMORY ...
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ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER V Power Supply Voltage DD V Power Supply Voltage (for I/O buffer) DDQ V Input Voltage IN V Output and I/O pin Voltage OUT V Input Reference Voltage REF T Operating Temperature (case) opr T ...
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Note: (1) All voltages referenced ( expected to track variations in V REF Peak to peak AC noise on V may not exceed 2% V REF (3) Overshoot limit (max) ...
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RECOMMENDED DC OPERATING CONDITIONS (V 2.5V 0.125V, V 1.4V ~ 1.9V DDQ SYMBOL PARAMETER Operating Current t min, I min ; CK RC Read/Write command cycling ; I DD1S (AC) (max ...
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RECOMMENDED DC OPERATING CONDITIONS (continued) (V 2.5V 0.125V, V 1.4V ~ 1.9V DDQ SYMBOL Input Leakage Current all other pins not under test IN DDQ Output Leakage Current I LO ...
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AC CHARACTERISTICS AND OPERATING CONDITIONS SYMBOL PARAMETER t Random Cycle Time RC t Clock Cycle Time CK t Random Access Time RAC t Clock High Time CH t Clock Low Time CL t DQS Access Time from CLK CKQS t ...
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AC CHARACTERISTICS AND OPERATING CONDITIONS SYMBOL PARAMETER t Data-out Low Impedance Time from CLK LZ t Data-out High Impedance Time from CLK HZ t DQS-out Low Impedance Time from CLK QSLZ t DQS-out High Impedance Time from CLK QSHZ t ...
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AC TEST CONDITIONS SYMBOL V Input High Voltage (minimum) IH (min) V Input Low Voltage (maximum) IL (max) V Input Reference Voltage REF V Termination Voltage TT V Input Signal Peak to Peak Swing SWING Vr Differential Clock Input Reference ...
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... If OCD calibration (Off Chip Driver impedance adjustment) is used, execute OCD calibration sequence. Notes: (1) Sequence 6, 7 and 8 can be issued in random order. (2) Set DQS mode for TC59LM906AMG. (3) L Logic Low, H Logic High (4) All DQs output level are high impedance state during power up sequence. ...
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... CLK 1st 1st t IS A0~A13 UA, BA BA0 BA2 Data DQS TC59LM906AMG enable mode DQS DQS DQ (input) Data DQS TC59LM906AMG disable mode TC59LM914AMG DQS DQ (input) Timing of the CLK, CLK CLK CLK CLK CLK V X TC59LM914/06AMG-37,- ...
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... TC59LM914AMG doesn’t have DQS . The correspondence of LDQS, UDQS to DQ. (TC59LM914AMG) LDQS UDQS DQS is Hi-Z in DQS disable mode. DQS mode is chosen by EMRS. (TC59LM906AMG) When DQS is enable, the condition of DQS is changed from Hi-Z to “High at Preamble and the condition of DQS is changed from “High” to Hi-Z at Postamble. TC59LM914/06AMG-37,-50 DESL ...
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... DQ (input) CAS latency 5 DQS/ DQS (input) DQ (input) Note: TC59LM914AMG doesn’t have DQS . The correspondence of LDQS, UDQS to DQ. (TC59LM914AMG) UDQS DQS is ignored in DQS disable mode. DQS mode is chosen by EMRS. (TC59LM906AMG) TC59LM914/06AMG-37,-50 DESL t DSPSTH t DSS DSP DSP DSP DSPST ...
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Ixxxx Timing REFI PAUSE CLK CLK Input (control & addresses) Command Note: “I ” means “I XXXX TC59LM914/06AMG-37,- REFI PAUSE XXXX ”, “I ”, “I ”, etc. ...
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Write Timing (x16 device) (Burst Length =4) CLK CLK Input WRA LAL (control & addresses) CAS latency 3 LDQS DQ0~DQ7 UDQS DQ8~DQ15 CAS latency 4 LDQS DQ0~DQ7 UDQS DQ8~DQ15 CAS latency 5 LDQS DQ0~DQ7 UDQS DQ8~DQ15 TC59LM914/06AMG-37,-50 DESL t t ...
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... LAL (2nd) H Note 5 : For x16 device “X” (either L or H). Write Command Table TC59LM914AMG COMMAND(SYMBOL) CS WRA (1st) L LAL (2nd) H TC59LM906AMG COMMAND(SYMBOL) CS WRA (1st) L LAL (2nd) H Notes: 6. BA2, A13 A11 are used for Variable Write Length (VW) control at Write Operation. TC59LM914/06AMG-37,- ...
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FUNCTION TRUTH TABLE (continued) VW Truth Table Burst Length Function Write All Words BL=2 Write First One Word Reserved Write All Words BL=4 Write First Two Words Write First One Word Note 7 : For x16 device, LVW0 and LVW1 ...
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FUNCTION TRUTH TABLE (continued) PD CURRENT STATE Idle Row Active for Read H L ...
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... Extended Mode Register is chosen using the combination of BA0 Extended Mode Register must be set to "0" to enable DLL for normal operation. 6. A11 in Extended Mode Register must be set to “0”. 7. TC59LM914AMG, A10 in Extended Mode Register is ignored. DQS is available only TC59LM906AMG. TC59LM914/06AMG-37,- BA2, A13~A8 A7 ...
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STATE DIAGRAM SELF- REFRESH AUTO- REFRESH REF ACTIVE (RESTORE) LAL TC59LM914/06AMG-37,-50 POWER DOWN SELFX PDEX ( PDEN ( PD L) STANDBY H (IDLE) WRA RDA ACTIVE LAL WRITE READ (BUFFER) MODE REGISTER ...
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TIMING DIAGRAMS SINGLE BANK READ TIMING ( CLK CLK cycles RC Command RDA LAL DESL cycle cycles RCD RAS Address UA LA Bank Add. #0 ...
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SINGLE BANK READ TIMING ( CLK CLK cycles RC Command RDA LAL DESL cycle cycles RCD RAS Address UA LA Bank Add ...
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SINGLE BANK READ TIMING ( CLK CLK cycles RC Command RDA LAL DESL cycle cycles RCD RAS Address UA LA Bank Add ...
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SINGLE BANK WRITE TIMING ( CLK CLK cycles RC Command WRA LAL DESL cycle cycles RCD RAS Address UA LA Bank Add ...
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SINGLE BANK WRITE TIMING ( CLK CLK cycles RC Command WRA LAL DESL cycle cycles RCD RAS Address UA LA Bank Add ...
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SINGLE BANK WRITE TIMING ( CLK CLK cycles RC Command WRA LAL DESL cycle cycles RCD RAS Address UA LA Bank Add ...
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SINGLE BANK READ-WRITE TIMING ( CLK CLK cycles RC Command RDA LAL DESL Address UA LA Bank Add Hi-Z DQS Hi-Z DQS Hi-Z DQ ...
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SINGLE BANK READ-WRITE TIMING ( CLK CLK cycles RC Command RDA LAL DESL Address UA LA Bank Add Hi-Z DQS Hi-Z DQS Hi-Z DQ ...
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SINGLE BANK READ-WRITE TIMING ( CLK CLK cycles RC Command RDA LAL DESL Address UA LA Bank Add Hi-Z DQS Hi-Z DQS Hi-Z DQ ...
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MULTIPLE BANK READ TIMING ( CLK CLK cycles RBD Command RDA LAL RDA LAL Address Bank Bank Bank Add. "a" "b" I (Bank"a" cycles RC ...
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MULTIPLE BANK READ TIMING ( CLK CLK cycles RBD Command RDA LAL RDA LAL Address Bank Bank Bank Add. "a" "b" I (Bank"a" cycles RC ...
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MULTIPLE BANK READ TIMING ( CLK CLK cycles RBD Command RDA LAL RDA LAL Address Bank Bank Bank Add. "a" "b" I (Bank"a" cycles RC ...
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MULTIPLE BANK WRITE TIMING ( CLK CLK cycles RBD Command WRA LAL WRA LAL Address Bank Bank Bank Add. "a" "b" I (Bank"a" cycles RC ...
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MULTIPLE BANK WRITE TIMING ( CLK CLK cycles RBD Command WRA LAL WRA LAL Address Bank Bank Bank Add. "a" "b" I (Bank"a" cycles RC ...
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MULTIPLE BANK WRITE TIMING ( CLK CLK cycles RBD Command WRA LAL WRA LAL Address Bank Bank Bank Add. "a" "b" I (Bank"a" cycles RC ...
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MULTIPLE BANK READ-WRITE TIMING ( CLK CLK cycles RBD cycle Command WRA LAL RDA LAL DESL WRD cycle cycles I WRD RWD ...
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MULTIPLE BANK READ-WRITE TIMING ( CLK CLK cycles RBD cycle Command WRA LAL RDA LAL WRD cycle I WRD RWD Address ...
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WRITE with VARIAVLE WRITE LENGTH (VW) CONTROL ( CLK CLK BL 2, SEQUENTIAL MODE Command WRA LAL DESL LA=#3 Address UA VW=All VW0 = Low VW1 = don't care Bank Bank Add. "a" DQS/ DQS (input) ...
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POWER DOWN TIMING (CL Read cycle to Power Down Mode CLK CLK Command RDA LAL Address Hi-Z DQS (output) Hi-Z DQS (output Hi-Z (output) Note: PD must be kept "High" ...
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POWER DOWN TIMING ( Write cycle to Power Down Mode CLK CLK Command WRA LAL Address DQS (input) DQS (input (input) Note: PD must be ...
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MODE REGISTER SET TIMING (CL From Read operation to Mode Register Set operation CLK CLK Command RDA LAL DESL A13~ BA0~BA2 BL/2 Hi-Z DQS (output) Hi-Z DQS DQ (output) Note: Minimum ...
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MODE REGISTER SET TIMING (CL From Write operation to Mode Register Set operation CLK CLK Command WRA LAL DESL A13~ BA0~BA2 BA WL+BL/2 DQS (input) DQS (input) DQ (input) Note: Minimum delay from LAL ...
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EXTENDED MODE REGISTER SET TIMING (CL From Read operation to Extended Mode Register Set operation CLK CLK Command RDA LAL DESL A13~ BA0~BA2 BL/2 Hi-Z DQS (output) DQS Hi-Z (output) DQ ...
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EXTENDED MODE REGISTER SET TIMING (CL From Write operation to Extended Mode Register Set operation CLK CLK Command WRA LAL DESL A13~ BA0~BA2 BA WL+BL/2 DQS (input) DQS (input) DQ (input) Note: DLL switch ...
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AUTO-REFRESH TIMING ( CLK CLK I 5 cycles RC Command RDA LAL Bank, Bank, Address cycle I RCD RAS DQS/ DQS Hi-Z (output) Hi-Z DQ (output) Note: In case ...
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SELF-REFRESH ENTRY TIMING CLK CLK I 1 cycle RCD Command WRA REF t t FPDL (min) FPDL (max QPDH Hi-Z DQS/ DQS (output) DQ Hi-Z Qx (output) Notes don’t care must ...
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FUNCTIONAL DESCRIPTION TM Network FCRAM TM FCRAM is an acronym of Fast Cycle Random Access Memory. The Network FCRAM perform fast random core access, low latency and high-speed data transfer. PIN FUNCTIONS CLOCK INPUTS: CLK & CLK The CLK and ...
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... DQS used as an input signal is utilized for a latch of write data. In read operation, the DQS is an output signal provides the read data strobe. TC59LM906AMG has differential data strobe pin ( DQS ). When DQS is enable mode, DQS is differential output signal for DQS in read operation, data input are latched at the crossing point of DQS and DQS in Write operation ...
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... Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for two clock cycle after PD goes high. The Power Down exit function is asynchronous operation. TC59LM914/06AMG-37,-50 2nd command RDA LAL) . DQS is differential data strobe signal supported TC59LM906AMG. RC 2nd command WRA LAL) ...
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Mode Register Set (MRS) and Extended Mode Register Set (EMRS) (1st command 2nd command When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register point to ...
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Addressing sequence of Sequential mode A column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. CAS Latency 4 CLK CLK Command RDA LAL DQS/ DQS DQ Addressing sequence ...
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Extended Mode Register fields (E-1) DLL Switch field (A0), (DS) This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled. This bit must set to “0” for normal operation. (E-2) Output Driver Impedance ...
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Extended Mode Register Set for OCD Impedance adjustment OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by Network FCRAM. In drive (1) mode, all DQ, DQS signals are driven ...
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... OIT 0 12ns (E-4) DQS enable field (A10), ( DQS ) This bit is used to enable Differential Data strobe. DQS is available on TC59LM906AMG. This field of TC59LM914AMG is ignored. (E-5) Interface mode select (A11) This bit must be always set “0”. (E-6) Reserved field (A2 to A5, A12 to A13, BA2) These bits are reserved for future operations and must be set to “0” for normal operation. ...
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PACKAGE DIMENSIONS P-BGA64-1317-1.00AZ Note: In order to support a package, four outer balls located on F and K row are required to assembly to board. These four ball is not connected to any electrical level. Weight: 0.23g (typ.) TC59LM914/06AMG-37,-50 16.5 ...
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REVISION HISTORY Rev.0.9 (Feb. 27 ’2004) Rev0.91 (Mar. 16 ‘2004) Corrected TYPO (page57). Pin name is changed from “Q” to “R”. Rev0.92 (Apr. 21 ‘2004) Parameter definition in Recommended DC, AC Operating Conditions Table are changed (page 5). V (DC): ...
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RESTRICTIONS ON PRODUCT USE N The information contained herein is subject to change without notice. N The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any ...