tc59lm906amg TOSHIBA Semiconductor CORPORATION, tc59lm906amg Datasheet - Page 48

• Manufacturer Part Number: tc59lm906amg
• Description: Mos Digital Integrated Circuit Silicon Monolithic
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DQS/ DQS
SELF-REFRESH ENTRY TIMING
SELF-REFRESH EXIT TIMING
DQS/ DQS
Command
Command
(output)
(output)
(output)
(output)
CLK
CLK
CLK
CLK
DQ
PD
PD
DQ
Notes: 1.
Notes: 1.
*2
Qx
WRA
t
I
QPDH
Self-Refresh Exit
RCD
t
0
FPDL (min)
0
Hi-Z
Hi-Z
2. Clock should be stable prior to PD
3. DESL command must be asserted during I
4. I
5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
6. Any command (except Read command) can be issued after I
7. Read command (RDA  LAL) can be issued after I
8. TC59LM914AMG doesn’t have DQS .
2. PD must be brought to "Low" within the timing between t
3. It is desirable that clock input is continued at least l
4. TC59LM914AMG doesn’t have DQS .
5. In the case of Self-Refresh entry after Write Operation, the delay time from the LAL command
mode. When PD is brought to "Low" after l
down mode. In case of PD fall between t
Self-Refresh mode or Power down mode after Auto-Refresh operation. It can’t be specified which
mode FCRAM operates.
brought to “Low” for Self-Refresh Entry.
following WRA to the REF command is Write Latency (WL) +3 clock cycles minimum.
other operation.
PDA
I
1 cycle
PDA
REF
t
1
PDEX
1
is defined from the first clock rising edge after PD is brought to “High”.
is don’t care.
DESL
is don’t care.
t
FPDL (max)
1 cycles
I
Hi-Z
Hi-Z
REFC
*3
2
2
*4
WRA
m  1
I
RCD
3
Self Refresh Entry
*5
Auto Refresh
REF
1 cycle
m
4
I
*5
REFC
I
I
PDV
CKD
DESL
m  1
“High” if clock input is suspended in Self-Refresh mode.
*2
5
I
FPDL
LOCK
REFC
DESL
I
PDV
REFC
(max) and l
, FCRAM perform Auto Refresh and enter Power
m  2
m  1
after PD is brought to “High”.
LOCK
CKD
from REF command even though PD is
.
I
FPDL
n  1
RCD
PDV
TC59LM914/06AMG-37,-50
m
REFC
(min) and t
, FCRAM will either entry
1 cycle
Command (1st)
m  1
.
n
Command (2nd)
FPDL
n  1
(max) to Self Refresh
2004-08-20 48/59
*6
RDA
p  1
*7
*6
LAL
Rev 1.0
p
*7