ak5352 AKM Semiconductor, Inc., ak5352 Datasheet - Page 12

• Manufacturer Part Number: ak5352
• Description: 96khz Sampling 20bit Adc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
Audio Serial Interface has four kinds of mode, it can be changed by SMODE1 and SMODE2 pins. Data format
is MSB first, 2's complement.
1) SLAVE mode
An output channel is defined by LRCK. Both channel data are output in sequence, in order of the Lch first then
Rch at the rate of fs. Data bits are clocked out via the SDATA pin at SCLK rate. Figure 1 and Figure 3 shows
data output timing at SCLK=64fs. FSYNC enables SCLK to start clocking out data. The MSB is clocked out by
the LRCK edge. SCLK causes the ADC to output succeeding bits when FSYNC is high. However, as I
mode ignores FSYNC, it should hold "L" or "H".
2) MASTER mode
In MASTER mode, the A/D converter is driven from a master clock(MCLK:256fs/384fs) and outputs all other
clocks(LRCK, SCLK). The falling edge of SCLK causes the ADC to output each bit. Figure 2 and Figure 4
shows the output timing. 2x fs clock of 50% duty is output via the FSYNC pin. FSYNC rises one SCLK cycle
after the transition of LRCK edges and stays high during 16 serial clocks(16*t
during FSYNC "H", lower 4 bit is output after FSYNC "L" transition.
0155-E-00
Serial Data Interface
Figure 1
Figure 2
Figure 3
Figure 4
Figure
SMODE1
H
H
L
L
Figure 1 . Data Output Timing (Slave mode)
SMODE2
H
H
L
L
Table 2 . Serial Interface
Slave Mode: 20bit, MSB justified
Master Mode: Similar to I
Slave Mode: I
Master Mode: I
- 12 -
2
S
2
Mode
S
2
S
SLK
). Upper 16 bit data is output
Lch=H, Rch=L
Lch=L, Rch=H
Lch=L, Rch=H
Lch=H, Rch=L
L/R polarity
2
S slave
[AK5352]
1997/1