ak5352 AKM Semiconductor, Inc., ak5352 Datasheet - Page 14

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ak5352

Manufacturer Part Number
ak5352
Description
96khz Sampling 20bit Adc
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
The AK5352 has to be reset once by bringing
and so on in the AK5352 are reset by this operation. When exiting the power-down mode(
internal timing starts clocking by first MCLK " "(rising edge). In master mode internal counter starts at once, in
slave mode internal counter starts after synchronizing with the first rising edge of LRCK. The serial output data
is available after 516 counting clock of LRCK cycle.
In slave mode, if the phase difference between LRCK and internal control signals is larger than +1/16
of word period(1/fs), the synchronization of internal control signals with LRCK is done automatically at the first
rising edge of LRCK.
The AK5352 has a Digital High Pass Filter(HPF) for DC-offset cancel. When HPFE pin goes "H", HPF is
enabled. The cut-off frequency of the HPF is 1Hz(@fs=48kHz). It also scales with the sampling frequency(fs).
The HPF can be disabled by bringing HPFE pin "L". In this case, the AK5352 has the DC-offset of a few mV.
0155-E-00
Power-down mode
Asynchronization-reset
High Pass Filter(HPFE pin)
PD
"L" upon power-up. All internal registers of the digital filter
- 14 -
PD
="H"), the
[AK5352]
-1/16
1997/1

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