ak5352 AKM Semiconductor, Inc., ak5352 Datasheet - Page 9

• Manufacturer Part Number: ak5352
• Description: 96khz Sampling 20bit Adc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
0155-E-00
Note 18 : Refer to Serial Data Interface.
Note 19 : Specified LRCK and FSYNC edges not to coincide with the rising edges of SCLK.
Note 20 : The number of LRCK rising edges after PD brought high. The value is in master mode.
Control Clock Frequency
Serial Interface Timing
Power down timing
SWITCHING CHARACTERISTICS
(Ta=25
Master Clock
Serial Data Output Clock
Channel Select Clock(Sampling Frequency)
Slave Mode(SMODE1="L")
Master Mode(SMODE1="H")
PD
PD
SCLK Period
SCLK Pulse width Low
SCLK Rising to LRCK Edge
LRCK Edge to SCLK Rising
LRCK Edge to SDATA MSB Valid
SCLK Falling to SDATA Valid
SCLK Rising to FSYNC Edge (Note 19 )
FSYNC Edge to SCLK Rising (Note 19 )
SCLK Frequency
FSYNC Frequency
SCLK Falling to LRCK Edge
LRCK Edge to FSYNC Rising
SCLK Falling to SDATA Valid
SCLK Falling to FSYNC Edge
Duty Cycle
Pulse width
Rising to SDATA Valid
Pulse width High
Duty Cycle
Duty Cycle
C
In slave mode it becomes one LRCK clock(1/fs) longer.
384fs: (fs = 54kHz)
; VA,VD,VB=5.0V±5%; C
Pulse width Low
Pulse width High
Pulse width Low
Pulse width High
256fs: (fs = 98kHz)
Parameter
(Note 20 )
(Note 18 )
(Note 19 )
(Note 19 )
L
=20pF)
- 9 -
f
t
t
f
t
t
f
f
t
t
t
t
t
t
t
t
t
f
f
t
t
t
t
t
t
CLK
CLKL
CLKH
CLK
CLKL
CLKH
SLK
s
SLK
SLKL
SLKH
SLR
LRS
DLR
DSS
SF
FS
SLK
FSYNC
SLR
LRF
DSS
SF
PDW
PDV
Symbol
4.096
6.144
20.83
20.83
159.4
15.9
15.9
150
min
-20
-20
16
25
65
65
30
30
30
30
12.288
18.432
3.072
64fs
516
typ
2fs
48
50
50
1
25.088
20.736
6.144
max
98
75
50
50
20
50
20
[AK5352]
1997/1
MHz
MHz
MHz
Unit
kHz
1/fs
tslk
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%