ak5352 AKM Semiconductor, Inc., ak5352 Datasheet - Page 3

• Manufacturer Part Number: ak5352
• Description: 96khz Sampling 20bit Adc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
0155-E-00
No.
10
11
14
12
13
16
17
18
19
20
1
2
3
4
5
6
7
8
9
VREF
VA
TST1
TST2
TST3
TST4
VD
AINR+
AINR-
AGND
AINL+
AINL-
HPFE
DGND
PD
MCLK
SCLK
LRCK
FSYNC
Pin Name
I/O
I/O
I/O
I/O
O
-
-
-
-
I
I
I
I
I
I
I
Right channel analog negative input pin
Voltage Reference output pin
Test pin
Digital section Digital Ground pin
Power Down pin
Master Clock input pin
Serial Data Clock pin
Right channel analog positive input pin
Analog section Analog Power Supply, +5V
Analog section Analog Ground
Left channel analog positive input pin
Left channel analog negative input pin
High Pass Filter Enable pin
Digital section Digital Power Supply pin, +5V
L/R Channel Clock Select pin
Frame Synchronization Signal pin
Normally connected to VA with a 0.1uF ceramic capacitor in
parallel with a 10uF electrolytic capacitor.
Should be left floating.
"H": ON
"L": OFF
"L" brings the device into power-down mode. Must be done
once after power-on.
CMODE="H" : 384fs
CMODE="L" : 256fs
Data is clocked out at the falling edge of SCLK.
Slave mode: 64fs clock is input usually.
Master mode: SCLK outputs a 64fs clock.
SCLK stays low during the power-down mode(PD="L").
Slave mode: An fs clock is fed to this LRCK pin.
Master mode: LRCK output an fs clock.
LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H"
during reset when SMODE1 "H".
Slave mode: When "H", data bits are clocked out on SDATA.
Master mode: FSYNC outputs 2fs clock.
Stay low during the power-down mode(PD="L").
As I
"H".
2
S slave mode ignores FSYNC, it should hold "L" or
PIN/FUNCTION
- 3 -
FUNCTION
(Pull-down pin)
(Pull-up pin)
(VA-2.6V)
[AK5352]
1997/1