sc16c850iet NXP Semiconductors, sc16c850iet Datasheet - Page 12

• Manufacturer Part Number: sc16c850iet
• Description: Sc16c850 2.5 V To 3.3 V Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda , And 16 Mode Or 68 Mode Parallel Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C850_1
Product data sheet
6.5 Hardware flow control
6.6 Software flow control
When automatic hardware flow control is enabled, the SC16C850 monitors the CTS pin
for a remote buffer overflow indication and controls the RTS pin for local buffer overflows.
Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C850 will suspend TX
transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTS input returns to a logic 0, indicating more data may
be sent.
When AFCR1[2] is set to logic 1 then the function of CTS pin is mapped to the DSR pin,
and the function of RTS is mapped to DTR pin. DSR and DTR pins will behave as
described above for CTS and RTS.
With the automatic hardware flow control function enabled, an interrupt is generated when
the receive FIFO reaches the programmed trigger level. The RTS (or DTR) pin will not be
forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level.
However, the RTS (or DTR) pin will return to a logic 0 after the receive buffer (FIFO) is
unloaded to the next trigger level below the programmed trigger level. Under the above
described conditions, the SC16C850 will continue to accept data until the receive FIFO is
full.
When the TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the ‘first extra feature
register set’ are all zeroes, the hardware and software flow control trigger levels are set by
FCR[7:4]; see
When the TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature
register set’ contain any value other than 0x00, the hardware and software flow control
trigger levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines
how many bytes are in the receive FIFO before RTS (or DTR) is de-asserted or Xoff is
sent. The content in FLWCNTL determines how many bytes are in the receive FIFO
before RTS (or DTR) is asserted, or Xon is sent.
In 128-byte FIFO mode, hardware and software flow control trigger levels can be set to
any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always
be greater than FLWCNTL. The UART does not check for this condition automatically, and
if this condition is not met, spurious operation of the device might occur. When using
FLWCNTH and FLWCNTL, these registers must be initialized to proper values before
hardware or software flow control is enabled via the EFR register.
When software flow control is enabled, the SC16C850 compares one or two sequentially
received data characters with the programmed Xon or Xoff character value(s). If the
received character(s) match the programmed Xoff values, the SC16C850 will halt
transmission (TX) as soon as the current character(s) has completed transmission. When
a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if
receive interrupt is enabled) will be activated. Following a suspension due to a match of
the Xoff characters’ values, the SC16C850 will monitor the receive data stream for a
match to the Xon1/Xon2 character value(s). If a match is found, the SC16C850 will
resume operation and clear the flags (ISR[4]).
Table
2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
6.
Rev. 01 — 10 January 2008
SC16C850
© NXP B.V. 2008. All rights reserved.
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