sc16c850iet NXP Semiconductors, sc16c850iet Datasheet - Page 26

• Manufacturer Part Number: sc16c850iet
• Description: Sc16c850 2.5 V To 3.3 V Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda , And 16 Mode Or 68 Mode Parallel Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C850_1
Product data sheet
7.4 Interrupt Status Register (ISR)
Table 12.
[1]
The SC16C850 provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits.
data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 13.
Table 14.
FCR[5]
0
0
1
1
Priority
level
1
2
2
3
4
5
6
Bit
7:6
5:4
3:1
When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[5]
0
0
0
0
0
0
1
TX FIFO trigger levels
Interrupt source
Interrupt Status Register bits description
FCR[4]
0
1
0
1
ISR[4]
0
0
0
0
0
1
0
2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C850 mode.
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
INT priority bits 2:0. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (see
Rev. 01 — 10 January 2008
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
ISR[3]
0
0
1
0
0
0
0
TX FIFO trigger level (bytes) in 32-byte FIFO mode
16
8
24
30
ISR[2]
1
1
1
0
0
0
0
ISR[1]
1
0
0
1
0
0
0
Table 13 “Interrupt source”
ISR[0]
0
0
0
0
0
0
0
Table
Source of the interrupt
LSR (Receiver Line Status
Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding
Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal)/
Special character
CTS, RTS change of state
Section 6.4 “FIFO
13).
SC16C850
© NXP B.V. 2008. All rights reserved.
operation”).
shows the
[1]
26 of 53