sc16c850iet NXP Semiconductors, sc16c850iet Datasheet - Page 18

• Manufacturer Part Number: sc16c850iet
• Description: Sc16c850 2.5 V To 3.3 V Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda , And 16 Mode Or 68 Mode Parallel Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C850_1
Product data sheet
6.11.1 Conditions to enter Sleep mode
6.11.2 Conditions to resume normal operation
6.11 Sleep mode
6.12 Low power feature
Sleep mode is an enhanced feature of the SC16C850 UART. It is enabled when EFR[4],
the enhanced functions bit, is set and when IER[4] bit is set.
Sleep mode is entered when:
In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are
clocked using these clocks, the power consumption is greatly reduced.
Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLM.
SC16C850 resumes normal operation by any of the following:
If the device is awakened by one of the conditions described above, it will return to the
Sleep mode automatically after all the conditions described in
device will stay in Sleep mode until it is disabled by setting any channel’s IER bit 4 to a
logic 0.
When the SC16C850 is in Sleep mode and the host data bus (D[7:0], A[2:0], IOW, IOR,
CS) remains in steady state, either HIGH or LOW, the Sleep mode supply current will be
in the A range as specified in
toggling or floating then the sleep current will be higher.
A low power feature is provided by the SC16C850 to prevent the switching of the host data
bus from influencing the sleep current. When the pin LOWPWR is activated (logic HIGH),
the device immediately and unconditionally goes into Low power mode. All clocks are
stopped and most host interface pins are isolated to reduce power consumption. The
device only returns to normal mode when the LOWPWR pin is de-asserted. The pin can
be left unconnected because it has an internal pull-down resistor.
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Modem input pins are not toggling.
The serial data input line, RX, is idle for 4 character time (logic HIGH) and AFCR1[4]
is logic 0. When AFCR1[4] is logic 1 the device will go to sleep regardless of the state
of the RX pin (see
The TX FIFO and TX shift register are empty.
There are no interrupts pending.
The RX FIFO is empty.
Receives a start bit on RX pin.
Data is loaded into transmit FIFO.
A change of state on any of the modem input pins
2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 01 — 10 January 2008
Section 7.21
Table 36 “Static
for the description of AFCR1 bit 4).
characteristics”. If any of these signals is
Section 6.11.1
SC16C850
© NXP B.V. 2008. All rights reserved.
are met. The
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