sc16c850iet NXP Semiconductors, sc16c850iet Datasheet - Page 34

• Manufacturer Part Number: sc16c850iet
• Description: Sc16c850 2.5 V To 3.3 V Uart, 5 Mbit/s Max. With 128-byte Fifos, Infrared Irda , And 16 Mode Or 68 Mode Parallel Bus Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C850_1
Product data sheet
7.17 Flow Control Trigger Level High (FLWCNTH)
7.18 Flow Control Trigger Level Low (FLWCNTL)
7.19 Clock Prescaler (CLKPRES)
[1]
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control.
register bit settings; see
Table 27.
[1]
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control.
register bit settings; see
Table 28.
[1]
This register hold values for the clock prescaler.
Table 29.
Bit
7:0
Bit
7:0
Bit
7:4
3:0
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
Symbol
FLWCNTH[7:0]
Symbol
FLWCNTL[7:0]
Symbol
CLKPRES[7:4]
CLKPRES[3:0]
FLWCNTH register bits description
FLWCNTL register bits description
Clock Prescaler register bits description
2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 01 — 10 January 2008
Section
Section
Description
This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode
Description
This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode
Description
reserved
Clock Prescaler value. Reset to 0.
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Section
Section
Section
6.5.
6.5.
7.3.
7.3.
7.3.
Table 27
Table 28
shows the FLWCNTH
shows the FLWCNTL
SC16C850
© NXP B.V. 2008. All rights reserved.
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