wm9081 Wolfson Microelectronics plc, wm9081 Datasheet - Page 53
![no-image](/images/no-image-200.jpg)
wm9081
Manufacturer Part Number
wm9081
Description
Mono Dac With 2.6w Class Ab/d Speaker Driver, Dynamic Range Controller And Retune Mobile Parametric Equalizer
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM9081.pdf
(109 pages)
- Current page: 53 of 109
- Download datasheet (2Mb)
Pre-Production
DIGITAL AUDIO INTERFACE
w
The digital audio interface is used for inputting DAC data to the WM9081. The digital audio interface
uses three pins:
In Software Control mode, many different audio data formats can be selected. In Hardware Control
mode, only a limited range of formats is supported.
SOFTWARE CONTROL MODE
In Software Control mode, the clock signals BCLK and LRCLK can be configured individually as
inputs or outputs, enabling master or slave modes of operation.
The WM9081 receives either the Left channel or the Right channel data from a stereo digital audio
source. Four different audio data formats are supported:
PCM operation is supported using the DSP mode. All four of these modes are MSB first. They are
described in Audio Data Formats, below. Refer to the “Electrical Characteristics” section for timing
information.
The word length of the audio data can be selected; the WM9081 supports 8, 16, 20, 24 and 32 bit
word lengths. A-law and μ-law companding is supported in 8-bit mode.
Time Division Multiplexing (TDM) is available in all four data format modes. The WM9081 can be
programmed to receive data in any of up to four stereo time slots.
HARDWARE CONTROL MODE
In Hardware Control mode, the WM9081 operates in slave mode, where the clock signals BCLK and
LRCLK are both inputs. The only supported sample rate is 48kHz; the controlling device must ensure
that the clocks and the data input are consistent with this.
The data format is 16-bit I
channel selection is made using the SCIM/CHANNEL pin, as described in “Control Interface
(Hardware Mode)”.
Companding and TDM modes are not supported in Hardware Control mode.
•
•
•
•
•
•
•
DACDAT: DAC data input
LRCLK: Left/Right data alignment clock
BCLK: Bit clock, for synchronisation
Left justified
Right justified
I
DSP mode
2
S
2
S mode, as described in “Audio Data Formats” below. The Left/Right
PP, Rev 3.0, April 2009
WM9081
53
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