wm8580a Wolfson Microelectronics plc, wm8580a Datasheet - Page 44

• Manufacturer Part Number: wm8580a
• Description: Multichannel Codec With S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics plc

WM8580
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Table 34 DAC Sample Rate Selection
If DACs 2 and 3 source the PAIFRX, while DAC 1 sources the S/PDIFRx then to synchronize all
DACs together, the DAC rate generator needs to use a common LRCLK. In this case, the
PAIFRX_LRCLK should be used. This is done by setting register bit RX2DAC_MODE=1, allowing the
PAIF_LRCLK to be used to generate the sampling rate. In this case, the S/PDIF sampling rate must
be synchronised with PAIF_LRCLK. In addition, when using the S/PDIF receiver, the PLLACLK and
PLLBCLK are not available to the DACs, and the DAC_CLK applied to the DACs must be at a
standard audio rate.
Table 35 DAC Clock Control
DAC Data Source
DAC1 =PAIFRX
DAC1=SAIFRX
DAC1=S/PDIFRX
(DAC2/3 also used)
DAC1=S/PDIFRX
(DAC2/3 NOT used)
DAC1=S/PDIFRX
DAC 2/3 = PAIFRX
REGISTER
ADDRESS
Control 1
CLKSEL
DAC
R15
08h
0Fh
R8
BIT
1:0
8
RX2DAC_MODE
DAC_CLKSEL
LABEL
Clock used for DAC
rate Generator (fs)
PAIFRX_LRCLK
SAIFRX_LRCLK
SFRM_CLK or
PAIFRX_LRCLK
SFRM_CLK
PAIFRX_LRCLK
DEFAULT
00
0
Comments
DAC sample rate based on PAIF Rx
DAC sample rate based on SAIF Rx
RX2DAC_MODE bit selects between the
SFRM_CLK (default) and the
PAIFRX_LRCLK.
Set RX2DAC_MODE=0
Need to synchronise the DACs to use the a
common LRCLK.Set RX2DAC_MODE=1
and S/PDIF Rx sampling rate must be
synchronous to PAIF_LRCLK
DAC clock source
DAC oversampling rate and power down
control (only valid when DAC_SRC = 00,
DAC1 data sourced from S/PDIF receiver)
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
0 = SFRM_CLK determines
oversampling rate, DACs 2/3 powered
down
1 = PAIFRX_LRCLK determines
oversampling rate, DACs 2/3 source
PAIF Receiver
DESCRIPTION
PD, Rev 4.7, March 2009
Production Data
44