wm8580a Wolfson Microelectronics plc, wm8580a Datasheet - Page 50

• Manufacturer Part Number: wm8580a
• Description: Multichannel Codec With S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics plc

WM8580
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In master mode the BCLK and LRCLK driving the SAIF interface are generated by the Master Mode
Clock Gen module. The control of this module is described on page 22.
The clock supplied to the Master Mode Clock Gen module can be ADCMCLK, PLLACLK, PLLBCLK,
or MCLK. Selection is automatic and is based on the digital routing configuration. Figure 31 illustrates
the clock configuration and Table 41 gives some examples of clock routing based on digital routing
configuration.
If the digital routing is configured such that the SAIF Transmitter is sourcing the S/PDIF Receiver,
then PLLACLK is automatically selected, and it is recommended that the interface operate in master
mode. However, if the SAIF Transmitter sources something other than the S/PDIF Receiver and the
S/PDIF Receiver is powered up, then the PLLACLK and PLLBCLK are invalid for SAIF operation, so
the choice forced to MCLK (default) or ADCMCLK.
Figure 31 SAIF Interface Clock Configuration
Table 42 SAIF Clock Configuration Examples
Table 43 SAIF Master Mode Clock Control
Digital Routing
Configuration
SAIF Tx = S/PDIF RX
SAIF Tx = PAIF RX
REGISTER
ADDRESS
SAIF 1
R11
0Bh
BIT
7:6
SAIFMS_
Clock used by SAIF
Master Mode Clock
Generator
PLLACLK
MCLK
CLKSEL
LABEL
DEFAULT
11
Comments
Recommend to operate SAIF in master
mode
Set SAIFMS_CLKSEL = 11
SAIF Master Mode clock source
00 = ADCMCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
DESCRIPTION
PD, Rev 4.7, March 2009
Production Data
50