wm8580a Wolfson Microelectronics plc, wm8580a Datasheet - Page 80
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wm8580a
Manufacturer Part Number
wm8580a
Description
Multichannel Codec With S/pdif Transceiver
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8580A.pdf
(103 pages)
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SLAVE MODE
If the S/PDIF Rx interface is enabled, then an internal MCLK is generated at 256fs. This internal
clock will act as a source clock for ADC, DACs and PAIF. The user is required to supply input clocks
to the PAIFTX_BCLK and the PAIF_LRCLK.
If the PAIF or DACs source the S/PDIF Rx interface then the PAIFTX_BCLK and the PAIF_LRCLK
input clocks must be synchronous to clock driving the S/PDIF interface. If these clocks cannot be
guaranteed synchronous then this mode of operation is not recommended.
If the PAIF sources the ADC data, then the user must supply input clocks to ADCCLK,
PAIFTX_BCLK and the PAIF_LRCLK pins.
PD, Rev 4.7, March 2009
Production Data
80
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