isppacclk5510v-01tn48i Lattice Semiconductor Corp., isppacclk5510v-01tn48i Datasheet - Page 2

• Manufacturer Part Number: isppacclk5510v-01tn48i
• Description: In-system Programmable Clock Generator With Universal Fan-out Buffer
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
General Description and Overview
The ispClock5510 and ispClock5520 are in-system-programmable high-fanout PLL-based clock drivers designed
for use in high performance communications and computing applications. The ispClock5510 provides up to 10 sin-
gle-ended or five differential clock outputs, while the ispClock5520 provides up to 20 single-ended or 10 differential
clock outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVDS,
LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent pro-
grammable control of termination, slew-rate, and timing skew. All configuration information is stored on-chip in non-
volatile E
The ispClock5500’s PLL and divider systems supports the synthesis of clock frequencies differing from that of the
reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V-divid-
ers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feedback
may be taken from the output of any of the five V-dividers.
The core functions of all members of the ispClock5500 family are identical, the differences between devices being
restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional
block diagrams of the ispClock5510 and ispClock5520.
Table 1. ispClock5500 Family Members
Figure 1. ispClock5510 Functional Block Diagram
REFVTT
REFA+
REFA-
2
CMOS memory.
0
Profile Select
PS0
Control
1
DIVIDER
INPUT
(1-32)
PS1
2
(1-32)
ispClock5510
ispClock5520
M
N
3
TDI
FEEDBACK
DIVIDER
JTAG INTERFACE
Device
TMS
DETECT
DETECT
PHASE
LOCK
LOCK
TCK
TDO
FILTER
LOOP
RESET
Ref. Input Pairs
VCO
2
1
2
PLL_BYPASS
SKEW ADJUST
FEEDBACK
1
0
DIVIDERS
OUTPUT
(2-64)
(2-64)
(2-64)
(2-64)
(2-64)
V0
V1
V2
V3
V4
SGATE
OUTPUT ENABLE CONTROLS
ispClock5500 Family Data Sheet
Clock Outputs
OUTPUT ROUTING
GOE
MATRIX
10
20
OEX
OEY
CONTROL
SKEW
DRIVERS
OUTPUT
BANK_0A
BANK_0B
BANK_1A
BANK_1B
BANK_2A
BANK_2B
BANK_3A
BANK_3B
BANK_4A
BANK_4B