isppacclk5510v-01tn48i Lattice Semiconductor Corp., isppacclk5510v-01tn48i Datasheet - Page 26

• Manufacturer Part Number: isppacclk5510v-01tn48i
• Description: In-system Programmable Clock Generator With Universal Fan-out Buffer
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ispClock5500 Family Data Sheet
ispClock5500’s internal termination resistors are not available in these modes. Also note that output slew-rate con-
trol is not available in LVDS or LVPECL mode, and that these drivers always operate at a fixed slew-rate.
Polarity control (true/inverted) is available for all output drivers. In the case of single-ended output standards, the
polarity of each of the two output signals from each bank may be controlled independently. In the case of differen-
tial output standards, the polarity of the differential pair may be selected.
Suggested Usage
Figure 23 shows a typical configuration for the ispClock5500’s output driver when configured to drive an LVTTL or
LVCMOS load. The ispClock5500’s output impedance should be set to match the characteristic impedance of the
transmission line being driven. The far end of the transmission line should be left open, with no termination resis-
tors.
Figure 23. Configuration for LVTTL/LVCMOS Output Modes
ispClock5500
LVCMOS/LVTTL
Mode
Zo
Ro = Zo
LVCMOS/LVTTL
Receiver
Figure 24 shows a typical configuration for the ispClock5500’s output driver when configured to drive SSTL2,
SSTL3, or HSTL loads. The ispClock5500’s output impedance should be set to 40Ω for driving SSTL2 or SSTL3
loads and to the ≈20Ω setting for driving HSTL. The far end of the transmission line must be terminated to an
appropriate VTT voltage through a 50Ω resistor.
Figure 24. Configuration for SSTL2, SSTL3, and HSTL Output Modes
VTT
ispClock5500
RT=50
SSTL/HSTL
SSTL/HSTL
Mode
Receiver
Zo=50
Ro : 40Ω (SSTL)
≈20Ω (HSTL)
VREF
While supporting single-ended HSTL and SSTL outputs, the ispClock5500 does not support differential HSTL or
SSTL. Although complementary HSTL and SSTL signals may be generated by using both an inverted output and a
non-inverted output similarly configured, the resulting signal pair may not meet the JEDEC differential HSTL speci-
fications for common mode voltage or crossover voltage.
Figure 25 shows a typical configuration for the ispClock5500’s output driver when configured to drive LVDS or dif-
ferential LVPECL loads. The ispClock5500’s output impedance is disengaged when the driver is set to LVDS or
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