isppacclk5510v-01tn48i Lattice Semiconductor Corp., isppacclk5510v-01tn48i Datasheet - Page 31

• Manufacturer Part Number: isppacclk5510v-01tn48i
• Description: In-system Programmable Clock Generator With Universal Fan-out Buffer
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
ispClock5500 Family Data Sheet
When one moves from coarse skew mode to fine skew mode, the extra divide-by-two factor is removed from
between the VCO and the V-divider bank, halving the VCO’s effective operating frequency. To compensate for this
change, all of the V-dividers must be doubled to move the VCO back into its specified operating range and maintain
consistent output frequencies. The only situation in which this may be a problem is when a V-divider initially in
coarse mode has a value greater than 32, as the corresponding fine skew mode setting would be greater than 64,
which is not supported.
Skew Matching and Accuracy
Understanding the various factors which relate to output skew is essential for realizing optimal skew performance in
the ispClock5500 family of devices.
In the case where two outputs are identically configured, and driving identical loads, the maximum skew is defined
by t
which is specified as a maximum of 50ps. In Figure 28 the Bank1A and BANK2A outputs show the skew
SKEW,
error between two matched outputs.
Figure 28. Skew Matching Error Sources
2ns +/- (t
) +/- (t
)
SKEW
SKERR
+/- t
SKEW
BANK1A
(skew setting = 0)
BANK2A
(skew setting=0)
BANK3A
(skew setting = 2ns)
One can also program a user-defined skew between two outputs using the skew control units. Because the pro-
grammable skew is derived from the VCO frequency, as described in the previous section, the absolute skew is
very accurate. The typical error for any non-zero skew setting is given by the t
specification. For example, if
SKERR
one is in fine skew mode with a VCO frequency of 500MHz, and selects a skew of 8TU, the realized skew will be
2ns, which will typically be accurate to within +/-30 ps. An example of error vs. skew setting can be found in the
chart ‘Typical Skew Error vs. Setting’ in the typical performance characteristics section. Note that this parameter
adds to output-to-output skew error only if the two outputs have different skew settings. The Bank1A and Bank3A
outputs in Figure 28 show how the various sources of skew error stack up in this case. Note that if two or more out-
puts are programmed to the same skew setting, then the contribution of the t
skew error term does not apply.
SKERR
When outputs are configured or loaded differently, this also has an effect on skew matching. If an output is set to
support a different logic type, this can be accounted for by using the t
output adders specified in the Table
IOO
‘Switching Characteristics’. That table specifies the additional skew added to an output using LVPECL as a base-
line. For instance, if one output is specified as LVTTL (t
= 0.1ns), and another output is specified as LVPECL
IOO
(t
= 0ns), then one could expect 0.1ns of additional skew between the two outputs. This timing relationship is
IOO
shown in Figure 29a.
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