isppacclk5510v-01tn48i Lattice Semiconductor Corp., isppacclk5510v-01tn48i Datasheet - Page 29

• Manufacturer Part Number: isppacclk5510v-01tn48i
• Description: In-system Programmable Clock Generator With Universal Fan-out Buffer
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Additionally, internal E
external control pins.
When GOE is HIGH, all output drivers are forced into a high-Z state, regardless of any internal configuration. When
GOE is LOW, the output drivers may also be enabled or disabled on an individual basis, and optionally controlled
by the OEX and OEY pins. Internal E
enabled (when GOE pin is LOW), never enabled (permanently off), or selectively enabled by the state of either
OEX or OEY. Bringing GOE high will also disable the internal feedback driver and will result in a loss of lock.
Synchronous output gating is provided by ispClock5500 devices through the use of the SGATE pin. The SGATE pin
does not disable the output driver, but merely forces the output to either a high or low state, depending on the out-
put driver’s polarity setting. If the output driver polarity is true, the output will be forced LOW when SGATE is
brought LOW, while if it is inverted, the output will be forced HIGH. A primary feature of the SGATE function is that
the clock output is enabled and disabled synchronous to the selected internal clock source. This prevents the gen-
eration of partial, ‘runt’, output clock pulses, which would otherwise occur with simple combinatorial gating
schemes. The SGATE is available to all clock outputs and is selectable on a bank-by-bank basis.
Table 5 shows the behavior of the outputs for various combinations of the output enables, SGATE input, and
E
Table 5. Clock Output Enable Functions
Table 6. SGATE Function
Skew Control Units
Each of the ispClock5500’s clock outputs is supported by a skew control unit which allows the user to insert an indi-
vidually programmable delay into each output signal. This feature is useful when it is necessary to de-skew clock
signals to compensate for physical length variations among different PCB clock paths.
Unlike the skew adjustment features provided in many competing products, the ispClock5500’s skew adjustment
feature provides exact and repeatable delays which exhibit extremely low channel-to-channel and device-to-device
variation. This is achieved by deriving all skew timing from the VCO, which results in the skew increment being a lin-
ear function of the VCO period. For this reason, skews are defined in terms of ‘time units’ (TUs), which may be pro-
2
CMOS configuration.
• GOE – global output enable
• OEX, OEY – secondary output enable controls
• SGATE – synchronous output control
SGATE Bank Controlled by SGATE?
X
X
0
0
1
1
2
CMOS configuration bits are provided for the purpose of modifying the effects of these
GOE
X
0
0
0
0
0
1
OEX
X
X
X
X
X
0
1
2
CMOS configuration is used to establish whether the output driver is always
YES
YES
YES
YES
NO
NO
OEY
X
X
X
X
X
0
1
E
Enable on OEX
Enable on OEX
Enable on OEY
Enable on OEY
2
Always OFF
Configuration
Always ON
29
n/a
Output Polarity
Inverted
Inverted
Inverted
True
True
True
ispClock5500 Family Data Sheet
Clock Out
Clock Out
Clock Out
Output
High-Z
High-Z
High-Z
High-Z
Inverted Clock
Inverted Clock
Output
Clock
HIGH
Clock
LOW