a2f500m3b-1csh484 Actel Corporation, a2f500m3b-1csh484 Datasheet - Page 110

• Manufacturer Part Number: a2f500m3b-1csh484
• Description: Actel
• Manufacturer: Actel Corporation

SmartFusion Programming
In-Application Programming
4 - 6
Note:
Figure 4-1 • TRSTB Logic
In-application programming refers to the ability to reprogram the various flash areas under direct
supervision of the Cortex-M3.
Reprogramming the FPGA Fabric Using the Cortex-M3
In this mode, the Cortex-M3 is executing the programming algorithm on-chip. The IAP driver can be
incorporated into the design project and executed from eNVM or eSRAM. Actel provides working
example projects for SoftConsole, IAR, and Keil development environments. These can be downloaded
via the Actel Firmware Catalog. The new bitstream to be programmed into the FPGA can reside on the
user’s printed circuit board (PCB) in a separate SPI flash memory. Alternately, the user can modify the
existing projects supplied by Actel and, via custom handshaking software, throttle the download of the
new image and program the FPGA a piece at a time in real time. A cost-effective and reliable approach
would be to store the bitstream in an external SPI flash. Another option is storing a redundant bitstream
image in an external SPI flash and loading the newest version into the FPGA only when receiving an IAP
command. Since the FPGA I/Os are tristated or held at predefined or last known state during FPGA
programming, the user must use MSS I/Os to interface to external memories. Since there are two SPI
controllers in the MSS, the user can dedicate one to an SPI flash and the other to the particulars of an
application. The amount of flash memory required to program the FPGA always exceeds the size of the
eNVM block that is on-chip. The external memory controller (EMC) cannot be used as an interface to a
memory device for storage of a bitstream because its I/O pads are FPGA I/Os; hence they are tristated
when the FPGA is in a programming state.
JTAG_SEL
Standard ARM JTAG connectors do not have access to the JTAGSEL pin. Actel’s free Eclipse-
based IDE, Soft Console, automatically sets JTAGSEL via FlashPro4 to the appropriate state for
programming all memory regions.
VJTAG (1.5 V to 3.3. V nominal)
TRSTB
R e vi s i o n 3
TRSTB
FPGA TAP
Controller
Controller
TAP
Programming Control
Cortex-M3
FPGA