zl2006 Intersil Corporation, zl2006 Datasheet - Page 19

• Manufacturer Part Number: zl2006
• Description: Adaptive Digital Dc-dc Controller With Drivers And Current Sharing
• Manufacturer: Intersil Corporation

5.7 Switching Frequency and PLL
The ZL2006 incorporates an internal phase-locked
loop (PLL) to clock the internal circuitry. The PLL can
be driven by an external clock source connected to the
SYNC pin. When using the internal oscillator, the
SYNC pin can be configured as a clock source for
other Zilker Labs devices.
The SYNC pin is a unique pin that can perform
multiple functions depending on how it is configured.
The CFG pin is used to select the operating mode of
the SYNC pin as shown in Table 14. Figure 15
illustrates the typical connections for each mode.
Table 14. SYNC Pin Function Selection
Configuration A: SYNC OUTPUT
When the SYNC pin is configured as an output (CFG
pin is tied HIGH), the device will run from its internal
oscillator and will drive the resulting internal oscillator
signal (preset to 400 kHz) onto the SYNC pin so other
devices can be synchronized to it. The SYNC pin will
not be checked for an incoming clock signal while in
this mode.
Configuration B: SYNC INPUT
When the SYNC pin is configured as an input (CFG
pin is tied LOW), the device will automatically check
for a clock signal on the SYNC pin each time EN is
asserted.
synchronize with the rising edge of the external clock.
The incoming clock signal must be in the range of 200
kHz to 1.4 MHz and must be stable when the enable
pin is asserted. The clock signal must also exhibit the
necessary performance requirements (see Table 3). In
the event of a loss of the external clock signal, the
output voltage may show transient over/undershoot.
If this happens, the ZL2006 will automatically switch
to its internal oscillator and switch at a frequency close
to the previous incoming frequency.
CFG Pin
OPEN
HIGH
LOW
The
ZL2006’s
SYNC is configured as an input
Auto Detect mode
SYNC is configured as an output
f
SW
19
= 400 kHz
SYNC Pin Function
oscillator
will
then
ZL2006
Configuration C: SYNC AUTO DETECT
When the SYNC pin is configured in auto detect mode
(CFG pin is left OPEN), the device will automatically
check for a clock signal on the SYNC pin after enable
is asserted.
If a clock signal is present, The ZL2006’s oscillator
will then synchronize the rising edge of the external
clock. Refer to SYNC INPUT description.
If no incoming clock signal is present, the ZL2006 will
configure the switching frequency according to the
state of the SYNC pin as listed in Table 15. In this
mode, the ZL2006 will only read the SYNC pin
connection during the start-up sequence. Changes to
SYNC pin connections will not affect f
power (VDD) is cycled off and on.
Table 15. Switching Frequency Selection
If the user wishes to run the ZL2006 at a frequency not
listed in Table 15, the switching frequency can be set
using an external resistor, R
SYNC and SGND using Table 16.
SYNC Pin
Resistor
OPEN
HIGH
LOW
SYNC
, connected between
See Table 16
December 15, 2010
Frequency
200 kHz
400 kHz
1 MHz
SW
FN6850.1
until the