zl2006 Intersil Corporation, zl2006 Datasheet - Page 28

• Manufacturer Part Number: zl2006
• Description: Adaptive Digital Dc-dc Controller With Drivers And Current Sharing
• Manufacturer: Intersil Corporation

5.11
Loop compensation can be a time-consuming process,
forcing the designer to accommodate design trade-offs
related to performance and stability across a wide
range of operating conditions. The ZL2006 offers an
adaptive compensation mode that enables the user to
increase the stability over a wider range of loading
conditions by
compensation coefficients for changes in load current.
Table 23. Pin-strap Settings for Loop Compensation
5.12
The ZL2006 incorporates a non-linear response (NLR)
loop that decreases the response time and the output
voltage deviation in the event of a sudden output load
current step. The NLR loop incorporates a secondary
error signal processing path that bypasses the primary
error loop when the output begins to transition outside
of the standard regulation limits. This scheme results in
a higher equivalent loop bandwidth than what is
possible using a traditional linear loop.
When a load current step function imposed on the
output causes the output voltage to drop below the
lower regulation limit, the NLR circuitry will force a
positive correction signal that will turn on the upper
MOSFET and quickly force the output to increase.
Conversely, a negative load step (i.e. removing a large
load current) will cause the NLR circuitry to force a
negative correction signal that will turn on the lower
MOSFET and quickly force the output to decrease.
The ZL2006 has been pre-configured with appropriate
NLR settings that correspond to the loop compensation
settings in Table 23. Please refer to Application Note
AN32 for more details regarding NLR settings.
f
f
sw
f
sw
sw
/240 < f
/120 < f
/60 < f
Adaptive Compensation
Non-linear Response (NLR) Settings
FC0 Range
n
n
n
< f
< f
< f
automatically
sw
sw
sw
/30
/120
28
/60
adapting the loop
FC0 Pin
OPEN
HIGH
LOW
ZL2006
f
f
f
sw
sw
sw
Setting the loop compensation coefficients through the
I
coefficients to be stored in the device in order to utilize
adaptive loop compensation. This algorithm uses the
two sets of compensation coefficients to determine
optimal compensation settings as the output load
changes. Please refer to Application Note AN33 for
further details on PMBus commands.
2
/10 > f
/10 > f
/10 > f
C/SMBus interface allows for a second set of
5.13
The ZL2006 utilizes a closed loop algorithm to
optimize the dead-time applied between the gate
drive signals for the top and bottom FETs. In a
synchronous buck converter, the MOSFET drive
circuitry must be designed such that the top and
bottom MOSFETs are never in the conducting state
at the same time. Potentially damaging currents flow
in the circuit if both top and bottom MOSFETs are
simultaneously on for periods of time exceeding a
few nanoseconds. Conversely, long periods of time
in which both MOSFETs are off reduce overall
circuit efficiency by allowing current to flow in their
parasitic body diodes.
It is therefore advantageous to minimize this dead-
time to provide optimum circuit efficiency. In the
first order model of a buck converter, the duty cycle
is determined by the equation:
However, non-idealities exist that cause the real duty
cycle to extend beyond the ideal. Dead-time is one of
FC1 Range
f
f
f
zesr
zesr
zesr
Reserved
Reserved
Reserved
> f
> f
> f
zesr
zesr
zesr
sw
sw
sw
Efficiency Optimized Driver Dead-time
Control
D ≈
> f
> f
> f
/10
/10
/10
sw
sw
sw
/30
/30
/30
V
V
OUT
IN
December 15, 2010
FC1 Pin
OPEN
OPEN
OPEN
HIGH
HIGH
HIGH
LOW
LOW
LOW
FN6850.1