zl2006 Intersil Corporation, zl2006 Datasheet - Page 36

• Manufacturer Part Number: zl2006
• Description: Adaptive Digital Dc-dc Controller With Drivers And Current Sharing
• Manufacturer: Intersil Corporation

In order to enable phase spreading, all converters must
be synchronized to the same switching clock. The CFG
pin is used to set the configuration of the SYNC pin for
each device as described in Section 5.7 “Switching
Frequency and PLL” on Page 19.
Selecting the phase offset for the device is
accomplished by selecting a device address according
to the following equation:
For example:
The phase offset of each device may also be set to any
value between 0° and 360° in 22.5° increments via the
I
for further details.
6.12 Output Sequencing
A group of Digital-DC devices may be configured to
power up in a predetermined sequence. This feature is
especially useful when powering advanced processors,
FPGAs, and ASICs that require one supply to reach its
operating voltage prior to another supply reaching its
operating voltage in order to avoid latch-up from
occurring. Multi-device sequencing can be achieved by
configuring each device through the I
interface or by using Zilker Labs patented autonomous
sequencing mode.
Autonomous sequencing mode configures sequencing
by using events transmitted between devices over the
DDC bus. This mode is not available on current
sharing rails.
The sequencing order is determined using each
device’s
sequencing mode (configured using the CFG pin), the
devices must be assigned sequential SMBus addresses
with no missing addresses in the chain. This mode will
also constrain each device to have a phase offset
according to its SMBus address as described in Section
6.11 “Phase Spreading”.
The sequencing group will turn on in order starting
with the device with the lowest SMBus address and
2
C/SMBus interface. Refer to Application Note AN33
• A device address of 0x00 or 0x20 would
• A device address of 0x01 or 0x21 would
• A device address of 0x02 or 0x22 would
Phase offset = device address x 45°
configure no phase offset
configure 45° of phase offset
configure 90° of phase offset
SMBus
36
address.
Using
autonomous
2
C/SMBus
ZL2006
will continue through to turn on each device in the
address chain until all devices connected have been
turned on. When turning off, the device with the
highest SMBus address will turn off first followed in
reverse order by the other devices in the group.
Sequencing is configured by connecting a resistor from
the CFG pin to ground as described in Table 29. The
CFG pin is also used to set the configuration of the
SYNC pin as well as to determine the sequencing
method and order. Please refer to 5.7 “Switching
Frequency and PLL” for more details on the operating
parameters of the SYNC pin.
Multiple device sequencing may also be achieved by
issuing PMBus commands to assign the preceding
device in the sequencing chain as well as the device
that will follow in the sequencing chain. This method
places fewer restrictions on SMBus address (no need
of sequential address) and also allows the user to
assign any phase offset to any device irrespective of its
SMBus device address.
The Enable pins of all devices in a sequencing group
must be tied together and driven high to initiate a
sequenced turn-on of the group. Enable must be driven
low to initiate a sequenced turnoff of the group.
Refer to Application Note AN33 for details on
sequencing via the I
6.13 Fault Spreading
Digital DC devices can be configured to broadcast a
fault event over the DDC bus to the other devices in
the group. When a non-destructive fault occurs and the
device is configured to shut down on a fault, the device
will shut down and broadcast the fault event over the
DDC bus. The other devices on the DDC bus will shut
down together if configured to do so, and will attempt
to re-start in their prescribed order if configured to do
so.
2
C/SMBus interface.
December 15, 2010
FN6850.1