ox16cf950 ETC-unknow, ox16cf950 Datasheet - Page 25

• Manufacturer Part Number: ox16cf950
• Description: Cost Asynchronous Card
• Manufacturer: ETC-unknow

6.2
The three address lines select the various registers in the UART. Since there are more than 8 registers, selection of the registers
is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’:
1. LCR[7]=1 enables the divider latch registers DLL and DLM.
2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables
3. ACR[7]=1 enables access to the 950 specific registers.
4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 27.
OXFORD SEMICONDUCTOR LTD.
Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.
Register
650 mode
750 mode
950 mode
9-bit data
9-bit data
650/950
550/750
550/750
650/950
Name
MCR
Normal
Normal
access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.
LSR
MSR
THR
RHR
IER
FCR
SPR
Mode
Mode
LCR
Mode
Mode
mode
mode
ISR
DLM
DLL
Register Description Tables
1,2
3
3,5
3,4
1
3
4
3
1
3
Address
000
000
001
010
010
011
100
101
110
111
000
001
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
R
R
prescale
interrupt
Divisor
access
Bit 7
mask
Baud
Error
CTS
latch
Data
DCD
Table 21: Standard 550 Compatible Registers
RHR Trigger
RHR Trigger
Unused
enabled
Unused
FIFOs
Level
Level
Tx Empty
interrupt
Bit 6
break
mode
mask
RTS
IrDA
Tx
RI
Unused
XON-Any
Alternate
Special
Control
Detect
CTS &
Empty
Divisor latch bits [7:0] (Least significant byte)
Divisor latch bits [15:8] (Most significant byte)
Bit 5
Char.
sleep
mode
Force
parity
FIFO
(Enhanced mode)
Flow
THR
DSR
Size
RTS
Interrupt priority
Indexed control register offset value bits
THR Trigger
Temporary data storage register and
Level
Data to be transmitted
Unused
Internal
Enable
Unused
Break
Bit 4
Sleep
mode
Odd /
parity
Loop
Back
even
CTS
Rx
Data received
Framing
interrupt
Modem
(Int En)
Mode /
Trigger
Enable
enable
OUT2
Bit 3
Parity
mask
DMA
Error
Delta
DCD
Tx
OXCF950 DATA SHEET V1.1
Interrupt priority
(All modes)
interrupt
Number
RI edge
Trailing
Rx Stat
data bit
of stop
Bit 2
OUT1
Flush
Parity
9
mask
Error
THR
bits
th
Rx
interrupt
Overrun
THRE
Bit 1
Flush
mask
Error
Delta
RHR
RTS
DSR
Data length
Interrupt
interrupt
pending
RxRDY
RxRDY
Page 25
Enable
data bit
Bit 0
mask
FIFO
Delta
9
DTR
CTS
th
Tx