ox16cf950 ETC-unknow, ox16cf950 Datasheet - Page 30

• Manufacturer Part Number: ox16cf950
• Description: Cost Asynchronous Card
• Manufacturer: ETC-unknow

6.5
6.5.1
On the falling edge of a start bit, the receiver will wait for
1/2 bit and re-synchronise the receiver’s sampling clock
onto the centre of the start bit. The start bit is valid if the
SIN line is still low at this mid-bit sample and the receiver
will proceed to read in a data character. Verifying the start
bit prevents the receiver from assembling a false data
character due to a low going noise spike on the SIN input.
Once the first stop bit has been sampled, the received data
is transferred to the RHR and the receiver will then wait for
a low transition on SIN signifying the next start bit.
The receiver will continue receiving data even if the RHR is
full or the receiver has been disabled (see section 6.11.3)
in order to maintain framing synchronisation. The only
difference is that the received data does not get transferred
to the RHR.
6.5.2
The LCR specifies the data format that is common to both
transmitter and receiver. Writing 0xBF to LCR enables
access to the EFR, XON1, XOFF1, XON2 and XOFF2,
DLL and DLM registers. This value (0xBF) corresponds to
an unused data format. Writing the value 0xBF to LCR will
set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not
affected. Write the desired LCR value to exit from this
selection.
LCR[1:0]: Data length
LCR[1:0] Determines the data length of serial characters.
Note however, that these values are ignored in 9-bit data
framing mode, i.e. when NMR[0] is set.
LCR[2]: Number of stop bits
LCR[2] defines the number of stop bits per serial character.
OXFORD SEMICONDUCTOR LTD.
Table 29: LCR Stop Bit Number Configuration
Line Control & Status
Table 28: LCR Data Length Configuration
LCR[1:0]
LCR[2]
False Start Bit Detection
Line Control Register ‘LCR’
00
01
10
11
0
1
1
Data length
5,6,7,8
6,7,8
5
Data length
5 bits
6 bits
7 bits
8 bits
No. stop
bits
1.5
1
2
LCR[5:3]: Parity type
The selected parity type will be generated during
transmission and checked by the receiver, which may
produce a parity error as a result. In 9-bit mode parity is
disabled and LCR[5:3] is ignored.
LCR[6]: Transmission break
logic 0
logic 1
It is the responsibility of the software driver to ensure that
the break duration is longer than the character period for it
to be recognised remotely as a break rather than data.
LCR[7]: Divisor latch enable
logic 0
logic 1
6.5.3
This register provides the status of data transfer to CPU.
LSR[0]: RHR data available
logic 0
logic 1
LSR[1]: RHR overrun error
logic 0
logic 1
LSR[2]: Received data parity error
logic 0
logic 1
The flag will be set when the data item in error is at the top
of the RHR and cleared following a read of the LSR. In 9-
LCR[5:3]
Line Status Register ‘LSR’
Table 30: LCR Parity Configuration
xx0
001
011
101
111
Break transmission disabled.
Forces the transmitter data output SOUT low
to alert the communication terminal, or send
zeros in IrDA mode.
Access to DLL and DLM registers disabled.
Access to DLL and DLM registers enabled.
RHR is empty: no data available
RHR is not empty: data is available to be read.
No overrun error.
Data was received when the RHR was full. An
overrun error has occurred. The error is
flagged when the data would normally have
been transferred to the RHR.
No parity error in normal mode or 9
received data is ‘0’ in 9-bit mode.
Data has been received that did not have
correct parity in normal mode or 9
received data is ‘1 ’ in 9-bit mode.
OXCF950 DATA SHEET V1.1
Parity bit forced to 1
Parity bit forced to 0
Even parity bit
Odd parity bit
No parity bit
Parity type
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