ox16cf950 ETC-unknow, ox16cf950 Datasheet - Page 41

• Manufacturer Part Number: ox16cf950
• Description: Cost Asynchronous Card
• Manufacturer: ETC-unknow

loopback mode this bit reflects the flow control status rather
than the pin’s actual state.
ASR[3]: DTR
This is the complement of the actual state of the DTR# pin
when the device is not in loopback mode. The driver
software can determine if the remote transmitter is disabled
by DTR# out-of - band flow control by reading this bit. In
loopback mode this bit reflects the flow control status rather
than the pin’s actual state.
ASR[4]: Special character detected
logic 0
logic 1
This can be used to determine whether a level 5 interrupt
was caused by receiving a special character rather than an
XOFF. The flag is cleared following the read of the ASR.
ASR[5]: RESERVED
This bit is unused in the OXCF950 and reads ‘0’.
ASR[6]: FIFO size
logic 0
logic 1
Note: If FCR[0] = 0, the FIFOs are 1 deep.
ASR[7]: Transmitter Idle
logic 0
logic 1
This bit reflects the state of the internal transmitter. It is set
when both the transmitter FIFO and shift register are
empty.
6.11.2 FIFO Fill levels ‘TFL & RFL’
The number of characters stored in the THR and RHR can
be determined by reading th e TFL and RFL registers
respectively. As the UART clock is asynchronous with
respect to the processor, it is possible for the levels to
change during a read of these FIFO levels. It is therefore
recommended that the levels are read twice and compared
to check that the values obtained are valid. The values
should be interpreted as follows:
1.
2.
6.11.3 Additional Control Register ‘ACR’
The ACR register is located at offset 0x00 of the ICR
OXFORD SEMICONDUCTOR LTD.
The number of characters in the THR is no greater
than the value read back from TFL.
The number of characters in the RHR is no less than
the value read back from RFL.
No special character has been detected.
A special character has been received and is
stored in the RHR.
FIFOs are 16 deep if FCR[0] = 1.
FIFOs are 128 deep if FCR[0] = 1.
Transmitter is transmitting.
Transmitter is idle.
ACR[0]: Receiver disable
logic 0
logic 1
Changes to this bit will only be recognised following the
completion of any data reception pending.
ACR[1]: Transmitter disable
logic 0
logic 1
Changes to this bit will only be recognised following the
completion of any data transmission pending.
ACR[2]: Enable automatic DSR flow control
logic 0
logic 1
This bit provides another automatic out - of-band flow control
facility using the DSR# line.
ACR[4:3]: DTR# line configuration
When bits 4 or 5 of CKS (offset 0x03 of ICR) are set, the
transmitter 1x clock or the output of the baud rate
generator (Nx clock) are asserted on the DTR# pin,
otherwise the DTR# pin is defined as follows:
logic [00]
logic [01]
logic [10]
The receiver is enabled, receiving data and
storing it in the RHR.
The receiver is disabled. The receiver
continues to operate as normal to maintain the
framing synchronisation with the receive data
stream but received data is not stored into the
RHR. In-band flow control characters continue
to be detected and acted upon. Special
characters will not be detected.
The transmitter is enabled, transmitting any
data in the THR.
The transmitter is disabled. Any data in the
THR is not transmitted but is held. However,
in-band flow control characters may still be
transmitted.
Normal. The state of the DSR# line does not
affect the flow control.
Data transmission is prevented whenever the
DSR# pin is held inactive high.
DTR# is compatible with 16C450, 16C550,
16C650 and 16C750 (i.e. normal).
DTR# pin is configured to drive the active
OXCF950 DATA SHEET V1.1
DTR# pin is used for out - of-band flow
control. It will be forced inactive high if
the Receiver FIFO Level (‘RFL’)
reaches
threshold. DTR# line will be re-activated
when the RFL drops below the lower
threshold (see FCL & FCH).
low enable pin of an external RS485
buffer. In this configuration the DTR#
pin will be forced low whenever the
transmitter is not empty (LSR[6]=0),
otherwise DTR# pin is high.
the
upper
flow
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control