ox16cf950 ETC-unknow, ox16cf950 Datasheet - Page 29

• Manufacturer Part Number: ox16cf950
• Description: Cost Asynchronous Card
• Manufacturer: ETC-unknow

Register ‘LSR’ (see section 6.5.3). Interrupts can be
generated or DMA signals can be used to transfer data
to/from the FIFOs. The number of items in each FIFO may
also be read back from the transmitter FIFO level (TFL)
and receiver FIFO level (RFL) registers (see section
6.11.2).
6.4.1
FCR[0]: Enable FIFO mode
logic 0
logic 1
This bit should be enabled before setting the FIFO trigger
levels.
FCR[1]: Flush RHR
logic 0
logic 1
This is only operative when already in a FIFO mode. The
RHR is automatically flushed whenever changing between
Byte mode and a FIFO mode. This bit will return to zero
after clearing the FIFOs.
FCR[2]: Flush THR
logic 0
logic 1
DMA Transfer Signalling:
FCR[3]: DMA signalling mode / Tx trigger level enable
logic 0
logic 1
DMA signals are not bonded out in the OXCF950, so this
control only affects the transmitter trigger level in DMA
mode 0.
FCR[5:4]: THR trigger level
Generally in 450, 550, extended 550 and 950 modes these
bits are unused (see section 6.1 for mode definition). In
650 mode they define the transmitter interrupt trigger levels
and in 750 mode FCR[5] increases the FIFO size.
450, 550 and extended 550 modes:
The transmitter interrupt trigger levels are set to 1 and
FCR[5:4] are ignored.
650 mode:
In 650 mode the transmitter interrupt trigger levels are set
to the following values:
OXFORD SEMICONDUCTOR LTD.
FCR[5:4]
00
01
10
FIFO Control Register ‘FCR’
Byte mode.
FIFO mode.
No change.
Flushes the contents of the RHR
No change.
Flushes the contents of the THR, in the same
manner as FCR[1] does for the RHR.
DMA mode '0'.
DMA mode '1'.
Transmit Interrupt Trigger level
16
32
64
These levels only apply when in Enhanced mode and in
DMA mode 1 (FCR[3] = 1), otherwise the trigger level is set
to 1. A transmitter empty interrupt w ill be generated (if
enabled) if the TFL falls below the trigger level.
750 Mode:
In 750 compatible non-Enhanced (EFR[4]=0) mode,
transmitter trigger level is set to 1, FCR[4] is unused and
FCR[5] defines the FIFO depth as follows:
FCR[5]=0 Transmitter and receiver FIFO size is 16 bytes.
FCR[5]=1 Transmitter and receiver FIFO size is 128 bytes.
In non-Enhanced mode FCR[5] is only writable when
LCR[7] is set. Note that in Enhanced mode, the FIFO size
is also increased to 128 bytes when FCR[0] is set.
950 mode:
Setting ACR[5]=1 enables arbitrary transmitter trigger level
setting using the TTL register (see section 6.11.4), hence
FCR[5:4] are ignored.
FCR[7:6]: RHR trigger level
In 550, extended 550, 650 and 750 modes, the receiver
FIFO trigger levels are defined using FCR[7:6]. The
interrupt trigger level and upper flow control trigger level
where appropriate are defined by L2 in the table below. L1
defines the lower flow control trigger level where
applicable. Separate upper and lower flow control trigger
levels introduce a hysteresis element in in-band and out - of -
band flow control (see section 6.9).
In Byte mode (450 mode) the trigger levels are all set to 1.
In all cases, a receiver data interrupt will be generated (if
enabled) if the Receiver FIFO Level (‘RFL’) reaches the
upper trigger level L2.
950 Mode:
When 950 trigger levels are enabled (ACR[5]=1), more
flexible trigger levels can be set by writing to the TTL, RTL,
FCL and FCH (see section 6.11) hence ignoring FCR[7:6].
FCR
[7:6]
00
01
10
11
Table 26: Transmit Interrupt Trigger Levels
11
FIFO Size 128
Table 27: Receiver Trigger Levels
112
L1
16
32
1
650
OXCF950 DATA SHEET V1.1
112
120
L2
16
32
FIFO Size 128
L1
1
1
1
1
Mode
750
112
112
L2
32
64
1
FIFO Size 16
n/a
n/a
n/a
n/a
L1
550
Page 29
L2
14
1
4
8